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Synthesis of ASIC regular arrays for real-time image processing systems

https://doi.org/10.1007/bf00925829
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-17943-7_135openalex-snapshot
Systolic array synthesis by static analysis of program dependencies
inferredcites →https://doi.org/10.1007/978-1-4615-3570-6_15openalex-snapshot
DSP Specification Using the Silage Language
inferredcites →https://doi.org/10.1007/bf02477176openalex-snapshot
The mapping of linear recurrence equations on regular arrays
inferredcites →https://doi.org/10.1016/0167-6423(90)90082-oopenalex-snapshot
Synthesis of a new systolic architecture for the algebraic path problem
inferredcites →https://doi.org/10.1016/0167-8191(90)90164-5openalex-snapshot
Deriving ASIC architectures for the Hough transform
inferredcites →https://doi.org/10.1016/0743-7315(85)90029-2openalex-snapshot
Parallelism detection and transformation techniques useful for VLSI algorithms
inferredcites →https://doi.org/10.1109/arrays.1988.18077openalex-snapshot
Scheduling a system of affine recurrence equations onto a systolic array
inferredcites →https://doi.org/10.1109/arrays.1988.18081openalex-snapshot
HIFI: a functional design system for VLSI processing arrays
inferredcites →https://doi.org/10.1109/asap.1990.145452openalex-snapshot
Extensions to linear mapping for regular arrays with complex processing elements
inferredcites →https://doi.org/10.1109/edac.1990.136658openalex-snapshot
Open-ended system for high-level synthesis of flexible signal processors
inferredcites →https://doi.org/10.1109/iscas.1989.100742openalex-snapshot
Target architectures in the CATHEDRAL synthesis systems: objectives and impact
inferredcites →https://doi.org/10.1109/tcad.1987.1270243openalex-snapshot
ADVIS: A Software Package for the Design of Systolic Arrays
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/800015.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1201/9781003065760openalex-snapshot
Systolic Signal Processing Systems
inferredcites →https://doi.org/10.5555/949970.950032openalex-snapshot
Open-ended system for high-level synthesis of flexible signal processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4615-2762-6_7openalex-snapshot
Modeling Data Flow and Control Flow for DSP System Synthesis
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_1openalex-snapshot
Application-Driven Synthesis Methodologies for Real-Time Processor Architectures
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_6openalex-snapshot
Regular Array Synthesis for Image and Video Applications
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_7openalex-snapshot
Memory and Data-Path Mapping for Image and Video Applications
inferred← citeshttps://doi.org/10.1007/978-1-4615-3506-5_4openalex-snapshot
Compiler Techniques for Massive Parallel Architectures
inferred← citeshttps://doi.org/10.1007/bf00930639openalex-snapshot
Nonlinear transformations for high level regular array ASIC synthesis
inferred← citeshttps://doi.org/10.1007/bf02120034openalex-snapshot
Resource constrained scheduling of uniform algorithms
inferred← citeshttps://doi.org/10.1007/bf03005235openalex-snapshot
Outils spécialisés de synthèse VLSI pour algorithmes de traitement numérique du signal
inferred← citeshttps://doi.org/10.1016/0167-8191(90)90164-5openalex-snapshot
Deriving ASIC architectures for the Hough transform
inferred← citeshttps://doi.org/10.1016/b978-0-444-88790-0.50009-5openalex-snapshot
Mapping Algorithms onto VLSI Architectures
inferred← citeshttps://doi.org/10.1016/j.jpdc.2003.04.002openalex-snapshot
Mapping rectangular mesh algorithms onto asymptotically space-optimal arrays
inferred← citeshttps://doi.org/10.1109/78.575701openalex-snapshot
Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures
inferred← citeshttps://doi.org/10.1109/asap.1991.238894openalex-snapshot
The systematic design of a motion estimation array architecture
inferred← citeshttps://doi.org/10.1109/asap.1992.218575openalex-snapshot
ARREST: an interactive graphic analysis tool for VLSI arrays
inferred← citeshttps://doi.org/10.1109/asap.1993.397126openalex-snapshot
On synthesizing application-specific array architectures from behavioral specifications
inferred← citeshttps://doi.org/10.1109/asap.1997.606826openalex-snapshot
Determination of the processor functionality in the design of processor arrays
inferred← citeshttps://doi.org/10.1109/cmpeur.1992.218494openalex-snapshot
Correctness preserving transformations on the Hough algorithm
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641063openalex-snapshot
The Exploitation Of Global Operations In Affine Space-time Mapping
inferred← citeshttps://doi.org/10.5555/951513.951609openalex-snapshot
Affine transformations for multi-dimensional signal processing on ASIC regular arrays
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