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The mapping of linear recurrence equations on regular arrays

https://doi.org/10.1007/bf02477176
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-17943-7_133openalex-snapshot
Synthesis of systolic arrays for inductive problems
inferredcites →https://doi.org/10.1007/3-540-17943-7_135openalex-snapshot
Systolic array synthesis by static analysis of program dependencies
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_27openalex-snapshot
Digital Signal Processing Applications of Systolic Algorithms
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bf02477176openalex-snapshot
The mapping of linear recurrence equations on regular arrays
inferredcites →https://doi.org/10.1016/0304-3975(93)90326-oopenalex-snapshot
Computability of recurrence equations
inferredcites →https://doi.org/10.1016/0377-2217(88)90189-0openalex-snapshot
Theory of linear and integer programming
inferredcites →https://doi.org/10.1016/0743-7315(88)90030-5openalex-snapshot
Systematic designs of buffers in macropipelines of systolic arrays
inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot
Regular iterative algorithms and their implementation on processor arrays
inferredcites →https://doi.org/10.1109/arrays.1988.18077openalex-snapshot
Scheduling a system of affine recurrence equations onto a systolic array
inferredcites →https://doi.org/10.1109/arrays.1988.18080openalex-snapshot
Broadcast removal in systolic algorithms
inferredcites →https://doi.org/10.1109/arrays.1988.18084openalex-snapshot
Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays
inferredcites →https://doi.org/10.1109/iscas.1988.15512openalex-snapshot
PRESAGE, a tool for the design of low-cost systolic circuits
inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot
VLSI Array processors
inferredcites →https://doi.org/10.1109/tc.1982.1675929openalex-snapshot
On the Analysis and Synthesis of VLSI Algorithms
inferredcites →https://doi.org/10.1109/tc.1985.1676516openalex-snapshot
The Design of Optimal Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1112/blms/21.6.621openalex-snapshot
THEORY OF LINEAR AND INTEGER PROGRAMMING (Wiley-Interscience Series in Discrete Mathematics and Optimization)
inferredcites →https://doi.org/10.1145/318789.318815openalex-snapshot
Alpha du centaur
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/360827.360844openalex-snapshot
The parallel execution of DO loops
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/773453.808186openalex-snapshot
Data broadcasting in linearly scheduled array processors
inferredcites →https://doi.org/10.1145/800015.808186openalex-snapshot
Data broadcasting in linearly scheduled array processors
inferredcites →https://doi.org/10.2307/2314299openalex-snapshot
Algebre Lineaire et Geometrie Elementaire.
inferredcites →https://doi.org/10.2307/253980openalex-snapshot
Theory of Linear and Integer Programming

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44614-1_101openalex-snapshot
Placement of Linear Arrays
inferred← citeshttps://doi.org/10.1007/3-540-53504-7_93openalex-snapshot
Asynchronous functional parallel programs
inferred← citeshttps://doi.org/10.1007/3-540-55160-3_51openalex-snapshot
The palindrome systolic array revisited
inferred← citeshttps://doi.org/10.1007/3-540-55210-3_220openalex-snapshot
ALPHA DU CENTAUR: An environment for the design of systolic arrays
inferred← citeshttps://doi.org/10.1007/3-540-55895-0_420openalex-snapshot
On the loading, recovery and access of stationary data in systolic arrays
inferred← citeshttps://doi.org/10.1007/3-540-56891-3_40openalex-snapshot
PEI: a single unifying model to design parallel programs
inferred← citeshttps://doi.org/10.1007/3-540-57208-2_28openalex-snapshot
Loop parallelization in the polytope model
inferred← citeshttps://doi.org/10.1007/978-1-4020-8588-8_12openalex-snapshot
High-Level Synthesis of Loops Using the Polyhedral Model
inferred← citeshttps://doi.org/10.1007/978-1-4615-2762-6_7openalex-snapshot
Modeling Data Flow and Control Flow for DSP System Synthesis
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_5openalex-snapshot
On the Design of Two-Level Pipelined Processor Arrays
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_6openalex-snapshot
Regular Array Synthesis for Image and Video Applications
inferred← citeshttps://doi.org/10.1007/978-1-4615-3996-4_6openalex-snapshot
Affine Permutations of Matrices on Mesh-Connected Arrays
inferred← citeshttps://doi.org/10.1007/978-1-4757-6130-6_15openalex-snapshot
Regularising Transformations for Integral Dependencies
inferred← citeshttps://doi.org/10.1007/978-3-540-72521-3_11openalex-snapshot
On Control Signals for Multi-Dimensional Time
inferred← citeshttps://doi.org/10.1007/978-3-540-77704-5_19openalex-snapshot
Computationally Efficient Parallel Matrix-Matrix Multiplication on the Torus
inferred← citeshttps://doi.org/10.1007/978-3-642-35867-8_4openalex-snapshot
Multi-objective Processor-Set Selection for Computational Cluster-Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-76119-5_56openalex-snapshot
Wie kann man imperative Programme auf eine Systolisierung vorbereiten?
inferred← citeshttps://doi.org/10.1007/978-3-662-25209-3_17openalex-snapshot
Affine Timings for Systems of Affine Recurrence Equations
inferred← citeshttps://doi.org/10.1007/bf00925828openalex-snapshot
The ALPHA language and its use for the design of systolic arrays
inferred← citeshttps://doi.org/10.1007/bf00925829openalex-snapshot
Synthesis of ASIC regular arrays for real-time image processing systems
inferred← citeshttps://doi.org/10.1007/bf00925834openalex-snapshot
A systolic array for pyramidal algorithms
inferred← citeshttps://doi.org/10.1007/bf00930639openalex-snapshot
Nonlinear transformations for high level regular array ASIC synthesis
inferred← citeshttps://doi.org/10.1007/bf01192158openalex-snapshot
Geometrical tools to map systems of affine recurrence equations on regular arrays
inferred← citeshttps://doi.org/10.1007/bf01407835openalex-snapshot
Some efficient solutions to the affine scheduling problem. I. One-dimensional time
inferred← citeshttps://doi.org/10.1007/bf02106104openalex-snapshot
Mapping 3-D IIR digital filter onto systolic arrays
inferred← citeshttps://doi.org/10.1007/bf02311229openalex-snapshot
Towards systolizing compilation
inferred← citeshttps://doi.org/10.1007/bf02407035openalex-snapshot
Closed-form mapping conditions for the synthesis of linear processor arrays
inferred← citeshttps://doi.org/10.1007/bf03180023openalex-snapshot
Intégration sur plate-forme matérielle/logicielle de spécifications ‘C’ parallèles
inferred← citeshttps://doi.org/10.1007/bfb0002752openalex-snapshot
Solutions to the communication minimization problem for affine recurrence equations
inferred← citeshttps://doi.org/10.1007/bfb0002778openalex-snapshot
Typechecking of Pei expressions
inferred← citeshttps://doi.org/10.1007/bfb0027118openalex-snapshot
Automatic synthesis of parallel algorithms
inferred← citeshttps://doi.org/10.1007/bfb0032956openalex-snapshot
Mapping systolic algorithms on distributed memory computers
inferred← citeshttps://doi.org/10.1007/s002360050053openalex-snapshot
Undecidability of restricted uniform recurrence equations
inferred← citeshttps://doi.org/10.1007/s10766-021-00694-2openalex-snapshot
Monoparametric Tiling of Polyhedral Programs
inferred← citeshttps://doi.org/10.1016/0020-0190(93)90189-gopenalex-snapshot
Systolic partitioning algorithms
inferred← citeshttps://doi.org/10.1016/0165-6074(92)90137-vopenalex-snapshot
Parallel implementation of local averaging for image processing
inferred← citeshttps://doi.org/10.1016/0165-6074(95)00025-jopenalex-snapshot
Compiling for massively parallel architectures: a perspective
inferred← citeshttps://doi.org/10.1016/0167-6423(90)90082-oopenalex-snapshot
Synthesis of a new systolic architecture for the algebraic path problem
inferred← citeshttps://doi.org/10.1016/0167-739x(94)90027-2openalex-snapshot
PEI: A simple unifying model to design parallel programs
inferred← citeshttps://doi.org/10.1016/0167-8191(90)90164-5openalex-snapshot
Deriving ASIC architectures for the Hough transform
inferred← citeshttps://doi.org/10.1016/0167-8191(92)90063-dopenalex-snapshot
PEI: A language and its refinement calculus for parallel programming
inferred← citeshttps://doi.org/10.1016/0167-8191(92)90077-kopenalex-snapshot
Synthesis of size-optimal toroïdal arrays for the Algebraic Path Problem: A new contribution
inferred← citeshttps://doi.org/10.1016/0167-8191(92)90137-vopenalex-snapshot
Systolic designs for Aitken's root finding method
inferred← citeshttps://doi.org/10.1016/0167-8191(93)90104-sopenalex-snapshot
A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
inferred← citeshttps://doi.org/10.1016/0167-8191(94)90002-7openalex-snapshot
Automating non-unimodular loop transformations for massive parallelism
inferred← citeshttps://doi.org/10.1016/0167-8191(95)00069-0openalex-snapshot
Transformations of nested loops with non-convex iteration spaces
inferred← citeshttps://doi.org/10.1016/0167-9260(90)90017-uopenalex-snapshot
Automating the design of systolic arrays
inferred← citeshttps://doi.org/10.1016/0167-9260(92)90008-mopenalex-snapshot
The synthesis of control signals for one-dimensional systolic arrays
inferred← citeshttps://doi.org/10.1016/0167-9260(93)90012-2openalex-snapshot
An improved systolic algorithm for the algebraic path problem
inferred← citeshttps://doi.org/10.1016/0167-9260(95)00018-6openalex-snapshot
Communication code generation in systems of affine recurrence equations
inferred← citeshttps://doi.org/10.1016/0304-3975(93)90326-oopenalex-snapshot
Computability of recurrence equations
inferred← citeshttps://doi.org/10.1016/0743-7315(92)90111-yopenalex-snapshot
Transformation of broadcasts into propagations in systolic algorithms
inferred← citeshttps://doi.org/10.1016/b978-044482106-5/50025-9openalex-snapshot
Uniformisation Techniques for Reducible Integral Recurrence Equations
inferred← citeshttps://doi.org/10.1016/j.jpdc.2003.04.002openalex-snapshot
Mapping rectangular mesh algorithms onto asymptotically space-optimal arrays
inferred← citeshttps://doi.org/10.1016/j.jpdc.2008.08.004openalex-snapshot
A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)60178-3openalex-snapshot
Algorithm-Specific Parallel Processing with Linear Processing Arrays
inferred← citeshttps://doi.org/10.1016/s0167-8191(00)00039-9openalex-snapshot
Derivation of systolic algorithms for the algebraic path problem by recurrence transformations
inferred← citeshttps://doi.org/10.1016/s0167-9260(99)00018-8openalex-snapshot
A parallel VLSI architecture of Kalman-filter-based algorithms for signal reconstruction
inferred← citeshttps://doi.org/10.1016/s0747-7171(06)80005-2openalex-snapshot
Synthesis aspects in the design of efficient processor arrays from affine recurrence equations
inferred← citeshttps://doi.org/10.1023/a:1007554627716openalex-snapshot
Generation of Efficient Nested Loops from Polyhedra
inferred← citeshttps://doi.org/10.1023/a:1007559710855openalex-snapshot
Communication Optimization for Affine Recurrence Equations Using Broadcast and Locality
inferred← citeshttps://doi.org/10.1023/a:1008074021139openalex-snapshot
Automatic Generation of Modular Time-Space Mappings and Data Alignments
inferred← citeshttps://doi.org/10.1023/a:1008103504836openalex-snapshot
A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays
inferred← citeshttps://doi.org/10.1023/a:1025117523902openalex-snapshot
Parameterized Polyhedra and Their Vertices
inferred← citeshttps://doi.org/10.1023/a:1025165407063openalex-snapshot
Affine Dependence Classification for Communications Minimization
inferred← citeshttps://doi.org/10.1080/00207160210953openalex-snapshot
Space-Time Equations for Non-Unimodular Mappings
inferred← citeshttps://doi.org/10.1080/00207160802275944openalex-snapshot
Forty-three ways of systolic matrix multiplication
inferred← citeshttps://doi.org/10.1080/00207169608804462openalex-snapshot
parallel parsing from recurrence equations
inferred← citeshttps://doi.org/10.1080/00207169708804598openalex-snapshot
Algorithm transformations for computational and data broadcast
inferred← citeshttps://doi.org/10.1080/01495730008947353openalex-snapshot
Advanced Regular Array Design
inferred← citeshttps://doi.org/10.1080/01495730008947354openalex-snapshot
A LIBRARY FOR DOING POLYHEDRAL OPERATIONS
inferred← citeshttps://doi.org/10.1080/01495730108941442openalex-snapshot
EIGENVECTORS-BASED PARALLELISATION OF NESTED LOOPS WITH AFFINE DEPENDENCES
inferred← citeshttps://doi.org/10.1080/01495739908947373openalex-snapshot
EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
inferred← citeshttps://doi.org/10.1080/07408179808966433openalex-snapshot
A formalism to structure and parallelize the integration of cooperative engineering design tasks
inferred← citeshttps://doi.org/10.1080/1063719042000208854openalex-snapshot
Tools for Regularizing Array Designs
inferred← citeshttps://doi.org/10.1080/10637199308915436openalex-snapshot
THE DERIVATION OF UNIFORM RECURRENCE EQUATIONS FOR THE KNAPSACK PROBLEM
inferred← citeshttps://doi.org/10.1080/10637199308915449openalex-snapshot
ON THE EXPECTED EXECUTION TIME FOR A CLASS OF NON UNIFORM RECURRENCE EQUATIONS MAPPED ONTO 1D REGULAR ARRAYS
inferred← citeshttps://doi.org/10.1080/10637199408962545openalex-snapshot
SYSTOLIC MATRIX INVERSION USING A MONTE CARLO METHOD
inferred← citeshttps://doi.org/10.1080/10637199608915604openalex-snapshot
TIMESPACE MAPPING FOR REGULAR ARRAYS
inferred← citeshttps://doi.org/10.1109/12.508321openalex-snapshot
On uniformization of affine dependence algorithms
inferred← citeshttps://doi.org/10.1109/12.589218openalex-snapshot
Multirate VLSI arrays and their synthesis
inferred← citeshttps://doi.org/10.1109/43.739055openalex-snapshot
Hierarchical algorithm partitioning at system level for an improved utilization of memory structures
inferred← citeshttps://doi.org/10.1109/5.503297openalex-snapshot
Parallel image processing with the block data parallel architecture
inferred← citeshttps://doi.org/10.1109/71.473518openalex-snapshot
A general methodology of partitioning and mapping for given regular arrays
inferred← citeshttps://doi.org/10.1109/78.575701openalex-snapshot
Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures
inferred← citeshttps://doi.org/10.1109/78.960433openalex-snapshot
Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetching
inferred← citeshttps://doi.org/10.1109/92.238445openalex-snapshot
Modeling multidimensional data and control flow
inferred← citeshttps://doi.org/10.1109/acssc.2017.8335151openalex-snapshot
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies
inferred← citeshttps://doi.org/10.1109/asap.1990.145447openalex-snapshot
Scheduling affine parameterized recurrences by means of
inferred← citeshttps://doi.org/10.1109/asap.1990.145452openalex-snapshot
Extensions to linear mapping for regular arrays with complex processing elements
inferred← citeshttps://doi.org/10.1109/asap.1991.238894openalex-snapshot
The systematic design of a motion estimation array architecture
inferred← citeshttps://doi.org/10.1109/asap.1991.238911openalex-snapshot
Synthesis of systolic arrays by equation transformations
inferred← citeshttps://doi.org/10.1109/asap.1992.218540openalex-snapshot
Scheduling partitions in systolic algorithms
inferred← citeshttps://doi.org/10.1109/asap.1993.397153openalex-snapshot
A new formulation of the mapping conditions for the synthesis of linear systolic arrays
inferred← citeshttps://doi.org/10.1109/asap.1993.397164openalex-snapshot
Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis
inferred← citeshttps://doi.org/10.1109/asap.1994.331800openalex-snapshot
On the injectivity of modular mappings
inferred← citeshttps://doi.org/10.1109/asap.1994.331802openalex-snapshot
Data compiling for systems of affine recurrence equations
inferred← citeshttps://doi.org/10.1109/asap.1995.523640openalex-snapshot
Synthesis of multirate VLSI arrays
inferred← citeshttps://doi.org/10.1109/asap.2003.1212827openalex-snapshot
Switched memory architectures - moving beyond systolic arrays
inferred← citeshttps://doi.org/10.1109/aspdac.2003.1194996openalex-snapshot
Register aware scheduling for distributed cache clustered architecture
inferred← citeshttps://doi.org/10.1109/ats.1998.741629openalex-snapshot
On-line error detection schemes for a systolic finite-field inverter
inferred← citeshttps://doi.org/10.1109/ccece.1999.808205openalex-snapshot
A systolic architecture for channel equalization based on a piecewise linear fuzzy logic algorithm
inferred← citeshttps://doi.org/10.1109/cgo.2007.21openalex-snapshot
Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time
inferred← citeshttps://doi.org/10.1109/cluster.2011.28openalex-snapshot
Automatic Hybrid OpenMP + MPI Program Generation for Dynamic Programming Problems
inferred← citeshttps://doi.org/10.1109/edac.1991.206443openalex-snapshot
Affine transformations for multi-dimensional signal processing on ASIC regular arrays
inferred← citeshttps://doi.org/10.1109/fccm.2016.27openalex-snapshot
Loop Splitting for Efficient Pipelining in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/glsv.1991.143967openalex-snapshot
Designing VLSI systolic arrays with complex processing elements
inferred← citeshttps://doi.org/10.1109/hpec.2012.6408676openalex-snapshot
Efficient and scalable computations with sparse tensors
inferred← citeshttps://doi.org/10.1109/icacte.2008.174openalex-snapshot
Presenting a Systematic Method for LU Decomposition of a Matrix with Linear Systolic Arrays
inferred← citeshttps://doi.org/10.1109/icapp.1995.472184openalex-snapshot
Non-unimodular code generation for parallel machines
inferred← citeshttps://doi.org/10.1109/icapp.1997.651504openalex-snapshot
Eigenvectors-based parallelisation of nested loops with affine dependences
inferred← citeshttps://doi.org/10.1109/icassp.1991.150617openalex-snapshot
A folding transformation for VLSI IIR filter array design
inferred← citeshttps://doi.org/10.1109/icfem.2000.873800openalex-snapshot
Formal derivation of multilayered hardware/software structures
inferred← citeshttps://doi.org/10.1109/icpads.1994.590382openalex-snapshot
Avoiding data link and computational conflicts in mapping nested loop algorithms to lower-dimensional processor arrays
inferred← citeshttps://doi.org/10.1109/icpp.1993.167openalex-snapshot
Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays
inferred← citeshttps://doi.org/10.1109/icpp.1994.86openalex-snapshot
Derivation of Systolic Programs
inferred← citeshttps://doi.org/10.1109/icpp.2001.952064openalex-snapshot
Uniformization of affine dependence programs for parallel embedded system design
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370229openalex-snapshot
Scheduling in the Z-Polyhedral Model
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370291openalex-snapshot
Towards Optimal Multi-level Tiling for Stencil Computations
inferred← citeshttps://doi.org/10.1109/ipdpsw52791.2021.00042openalex-snapshot
Accelerating the BPMax Algorithm for RNA-RNA Interaction
inferred← citeshttps://doi.org/10.1109/ipps.1991.153840openalex-snapshot
A geometrical coding to compile affine recurrence equations on regular arrays
inferred← citeshttps://doi.org/10.1109/ipps.1993.262778openalex-snapshot
Mapping of uniform dependence algorithm onto fixed size processor arrays
inferred← citeshttps://doi.org/10.1109/ipps.1993.262863openalex-snapshot
Mapping a class of run-time dependencies onto regular arrays
inferred← citeshttps://doi.org/10.1109/ipps.1995.395863openalex-snapshot
On deriving data parallel code from a functional program
inferred← citeshttps://doi.org/10.1109/ipps.1995.395967openalex-snapshot
Toward data distribution independent parallel matrix multiplication
inferred← citeshttps://doi.org/10.1109/ipps.1996.508197openalex-snapshot
Mapping linear recurrences onto systolic arrays
inferred← citeshttps://doi.org/10.1109/mixdes.2016.7529786openalex-snapshot
Polyhedral Source-to-Source Compiler
inferred← citeshttps://doi.org/10.1109/mpcs.1994.367045openalex-snapshot
Experimental evaluation of affine schedules for matrix multiplication on the MasPar architecture
inferred← citeshttps://doi.org/10.1109/mwscas.1989.101866openalex-snapshot
User interface issues in CAD tools for systolic array design
inferred← citeshttps://doi.org/10.1109/pacrim.1991.160816openalex-snapshot
Systematic derivation of VLSI arrays for digital DSP algorithms
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00024openalex-snapshot
Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations
inferred← citeshttps://doi.org/10.1109/pccc.1995.472509openalex-snapshot
Parallel task scheduling using the order graph method
inferred← citeshttps://doi.org/10.1109/secon.1995.513107openalex-snapshot
Parallel task scheduling for the block data flow architecture
inferred← citeshttps://doi.org/10.1109/spdp.1992.242753openalex-snapshot
On uniformization of affine dependence algorithms
inferred← citeshttps://doi.org/10.1109/spdp.1993.395490openalex-snapshot
An algorithm to automate non-unimodular transformations of loop nests
inferred← citeshttps://doi.org/10.1109/synasc.2005.36openalex-snapshot
Functional-based synthesis of systolic online multipliers
inferred← citeshttps://doi.org/10.1109/tcad.2005.852431openalex-snapshot
Platform-based design from parallel C specifications
inferred← citeshttps://doi.org/10.1109/tcad.2017.2783363openalex-snapshot
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2019.2926489openalex-snapshot
Optimization Approach to Accelerator Codesign
inferred← citeshttps://doi.org/10.1109/tcad.2022.3201494openalex-snapshot
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout
inferred← citeshttps://doi.org/10.1109/tencon.1994.369239openalex-snapshot
SysPar: a software package for systolising and parallelising nested loop algorithms
inferred← citeshttps://doi.org/10.1109/tpds.2003.1167366openalex-snapshot
Generation of injective and reversible modular mappings
inferred← citeshttps://doi.org/10.1109/tpds.2024.3380443openalex-snapshot
Taking RNA-RNA Interaction to Machine Peak
inferred← citeshttps://doi.org/10.1109/trustcom.2013.125openalex-snapshot
The Buffered Edge Reconfigurable Cell Array and Its Applications
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641063openalex-snapshot
The Exploitation Of Global Operations In Affine Space-time Mapping
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641069openalex-snapshot
Piecewise Linear Schedules For Recurrence Equations
inferred← citeshttps://doi.org/10.1109/vlsisp.1994.574763openalex-snapshot
Distributed memory and control VLSI architectures for the 1-D Discrete Wavelet Transform
inferred← citeshttps://doi.org/10.1109/vlsisp.1994.574768openalex-snapshot
What is a multirate array?
inferred← citeshttps://doi.org/10.1142/s0129626494000247openalex-snapshot
DATA COMPILING FOR SYSTEMS OF UNIFORM RECURRENCE EQUATIONS
inferred← citeshttps://doi.org/10.1145/109625.109630openalex-snapshot
A unified framework for systematic loop transformations
inferred← citeshttps://doi.org/10.1145/1119772.1119787openalex-snapshot
Register aware scheduling for distributed cache clustered architecture
inferred← citeshttps://doi.org/10.1145/1286821.1286825openalex-snapshot
A step towards unifying schedule and storage optimization
inferred← citeshttps://doi.org/10.1145/1375657.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/1379023.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/2145694.2145727openalex-snapshot
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
inferred← citeshttps://doi.org/10.1145/277651.277691openalex-snapshot
Linear programming models for scheduling systems of affine recurrence equations---a comparative study
inferred← citeshttps://doi.org/10.1145/2837614.2837656openalex-snapshot
PolyCheck: dynamic verification of iteration space transformations on affine programs
inferred← citeshttps://doi.org/10.1145/3018743.3018744openalex-snapshot
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
inferred← citeshttps://doi.org/10.1145/3155284.3018744openalex-snapshot
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
inferred← citeshttps://doi.org/10.1145/318789.318815openalex-snapshot
Alpha du centaur
inferred← citeshttps://doi.org/10.1145/3446804.3446847openalex-snapshot
Data-aware process networks
inferred← citeshttps://doi.org/10.1145/365151.365152openalex-snapshot
Optimizing memory usage in the polyhedral model
inferred← citeshttps://doi.org/10.1145/3704839openalex-snapshot
Maximal Simplification of Polyhedral Reductions
inferred← citeshttps://doi.org/10.1145/502217.502228openalex-snapshot
Combined partitioning and data padding for scheduling multiple loop nests
inferred← citeshttps://doi.org/10.1145/564870.564888openalex-snapshot
Scheduling reductions on realistic machines
inferred← citeshttps://doi.org/10.1147/rd.445.0681openalex-snapshot
Parallel Image Processing with the Block Data Parallel Architecture
inferred← citeshttps://doi.org/10.1201/9781420040579.ch10openalex-snapshot
Dependence Analysis and Parallelizing Transformations
inferred← citeshttps://doi.org/10.1201/9781420043839.ch15openalex-snapshot
Computations on Iteration Spaces
inferred← citeshttps://doi.org/10.15199/13.2016.12.1openalex-snapshot
Polyhedral Source-to-Source Compile)
inferred← citeshttps://doi.org/10.2172/1422949openalex-snapshot
Analytical Cost Metrics : Days of Future Past
inferred← citeshttps://doi.org/10.2471/trs.02.935openalex-snapshot
Technical Report Series 935
inferred← citeshttps://doi.org/10.4236/jamp.2024.124075openalex-snapshot
Understanding the Theory of Karp, Miller and Winograd
inferred← citeshttps://doi.org/10.48550/arxiv.1610.07236openalex-snapshot
Hybrid Static/Dynamic Schedules for Tiled Polyhedral Programs
inferred← citeshttps://doi.org/10.48550/arxiv.1712.04892openalex-snapshot
Accelerator Codesign as Non-Linear Optimization
inferred← citeshttps://doi.org/10.48550/arxiv.1802.00166openalex-snapshot
PCOT: Cache Oblivious Tiling of Polyhedral Programs
inferred← citeshttps://doi.org/10.48550/arxiv.2010.03074openalex-snapshot
On Simplifying Dependent Polyhedral Reductions
inferred← citeshttps://doi.org/10.5555/951513.951609openalex-snapshot
Affine transformations for multi-dimensional signal processing on ASIC regular arrays
inferred← citeshttps://doi.org/10.70675/3cde6274ze889z4b94zb3c6z60783d4685c6openalex-snapshot
Detection of linear algebra operations in polyhedral programs
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