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Control generation in the design of processor arrays

https://doi.org/10.1007/bf00927836
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/9781118627372openalex-snapshot
Integer and Combinatorial Optimization
inferredcites →https://doi.org/10.1007/3-540-17943-7_135openalex-snapshot
Systolic array synthesis by static analysis of program dependencies
inferredcites →https://doi.org/10.1007/978-1-4613-9668-0_6openalex-snapshot
Parallel Program Design
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bf02427796openalex-snapshot
Parallel algorithms/architectures for neural networks
inferredcites →https://doi.org/10.1016/0167-8191(88)90095-6openalex-snapshot
The instruction systolic array and its relation to other models of parallel computers
inferredcites →https://doi.org/10.1016/0167-8191(90)90044-aopenalex-snapshot
Spacetime-minimal systolic arrays for Gaussian elimination and the Algebraic path problem
inferredcites →https://doi.org/10.1016/0743-7315(87)90041-4openalex-snapshot
A systolic array for cyclic-by-rows Jacobi algorithms
inferredcites →https://doi.org/10.1016/0743-7315(89)90008-7openalex-snapshot
A model for an intelligent operating system for executing image understanding tasks on a reconfigurable parallel architecture
inferredcites →https://doi.org/10.1016/0743-7315(89)90043-9openalex-snapshot
A reconfigurable fully parallel associative processor
inferredcites →https://doi.org/10.1016/0743-7315(89)90050-6openalex-snapshot
Linear systolic arrays for matrix computations
inferredcites →https://doi.org/10.1016/0743-7315(89)90057-9openalex-snapshot
Synthesizing minimum total expansion topologies for reconfigurable interconnection networks
inferredcites →https://doi.org/10.1109/12.8709openalex-snapshot
A systolic array for the assignment problem
inferredcites →https://doi.org/10.1109/2.48799openalex-snapshot
A taxonomy of reconfiguration techniques for fault-tolerant processor arrays
inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot
Regular iterative algorithms and their implementation on processor arrays
inferredcites →https://doi.org/10.1109/arrays.1988.18080openalex-snapshot
Broadcast removal in systolic algorithms
inferredcites →https://doi.org/10.1109/arrays.1988.18081openalex-snapshot
HIFI: a functional design system for VLSI processing arrays
inferredcites →https://doi.org/10.1109/asap.1990.145440openalex-snapshot
Systolic array implementation of nested loop programs
inferredcites →https://doi.org/10.1109/asic.1989.123165openalex-snapshot
Application-specific array processors
inferredcites →https://doi.org/10.1109/icassp.1987.1169583openalex-snapshot
One- and two-dimensional systolic arrays for least-squares problems
inferredcites →https://doi.org/10.1109/iscas.1988.15454openalex-snapshot
On the hierarchical design of VLSI processor arrays
inferredcites →https://doi.org/10.1109/iscas.1989.100823openalex-snapshot
On the design of piecewise regular processor arrays
inferredcites →https://doi.org/10.1109/iscas.1990.112262openalex-snapshot
Design of configurable processor arrays
inferredcites →https://doi.org/10.1109/mc.1982.1653826openalex-snapshot
Introduction to the configurable, highly parallel computer
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1117/12.942041openalex-snapshot
Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/800015.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.2307/2583737openalex-snapshot
Integer and Combinatorial Optimization

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/jnm.1660050308openalex-snapshot
Parallel implementation of cellular systems for numerical modelling
inferred← citeshttps://doi.org/10.1007/11682127_13openalex-snapshot
Controller Synthesis for Mapping Partitioned Programs on Array Architectures
inferred← citeshttps://doi.org/10.1007/3-540-45874-3_9openalex-snapshot
Generation of Distributed Loop Control
inferred← citeshttps://doi.org/10.1007/3-540-57208-2_28openalex-snapshot
Loop parallelization in the polytope model
inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_4openalex-snapshot
HIFI: From Parallel Algorithm to Fixed-Size VLSI Processor Array
inferred← citeshttps://doi.org/10.1007/978-1-4615-3506-5_4openalex-snapshot
Compiler Techniques for Massive Parallel Architectures
inferred← citeshttps://doi.org/10.1007/978-1-4757-6130-6_15openalex-snapshot
Regularising Transformations for Integral Dependencies
inferred← citeshttps://doi.org/10.1007/978-1-4757-9805-0_22openalex-snapshot
A Design System for Massively Parallel Hardware
inferred← citeshttps://doi.org/10.1007/978-3-319-73909-0_2openalex-snapshot
Fundamentals and Compiler Framework
inferred← citeshttps://doi.org/10.1007/978-3-540-46824-0_4openalex-snapshot
Ablaufplanung
inferred← citeshttps://doi.org/10.1007/978-3-642-77447-8_15openalex-snapshot
Rekursive Prozeduraufrufe in VLSI-Occam
inferred← citeshttps://doi.org/10.1007/bf00924523openalex-snapshot
VASS—A VLSI array system synthesizer
inferred← citeshttps://doi.org/10.1007/bf02407035openalex-snapshot
Closed-form mapping conditions for the synthesis of linear processor arrays
inferred← citeshttps://doi.org/10.1007/bfb0027118openalex-snapshot
Automatic synthesis of parallel algorithms
inferred← citeshttps://doi.org/10.1016/0165-6074(95)00020-oopenalex-snapshot
Algorithm-architecture co-design by example: a coprocessor for on-line arithmetic
inferred← citeshttps://doi.org/10.1016/0167-9260(93)90013-3openalex-snapshot
Partitioning of processor arrays: a piecewise regular approach
inferred← citeshttps://doi.org/10.1016/0167-9260(93)90021-4openalex-snapshot
Example of combined algorithm development and architecture design
inferred← citeshttps://doi.org/10.1016/b978-0-444-88790-0.50009-5openalex-snapshot
Mapping Algorithms onto VLSI Architectures
inferred← citeshttps://doi.org/10.1016/b978-044482106-5/50011-9openalex-snapshot
A Case Study in Algorithm-Architecture Codesign
inferred← citeshttps://doi.org/10.1016/b978-044482106-5/50025-9openalex-snapshot
Uniformisation Techniques for Reducible Integral Recurrence Equations
inferred← citeshttps://doi.org/10.1016/j.jpdc.2003.04.002openalex-snapshot
Mapping rectangular mesh algorithms onto asymptotically space-optimal arrays
inferred← citeshttps://doi.org/10.1016/j.sysarc.2006.10.009openalex-snapshot
Efficient control generation for mapping nested loop programs onto processor arrays
inferred← citeshttps://doi.org/10.1023/a:1007904422322openalex-snapshot
The Static Parallelization of Loops and Recursions
inferred← citeshttps://doi.org/10.1023/a:1008008231304openalex-snapshot
On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming
inferred← citeshttps://doi.org/10.1023/a:1024447517501openalex-snapshot
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms
inferred← citeshttps://doi.org/10.1109/76.143415openalex-snapshot
Parallel architecture for a pel-recursive motion estimation algorithm
inferred← citeshttps://doi.org/10.1109/78.575701openalex-snapshot
Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures
inferred← citeshttps://doi.org/10.1109/78.839983openalex-snapshot
Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction
inferred← citeshttps://doi.org/10.1109/acssc.2001.986970openalex-snapshot
Boundary control: a new distributed control architecture for space-time transformed (VLSI) processor arrays
inferred← citeshttps://doi.org/10.1109/asap.1992.218585openalex-snapshot
A transformative approach to the partitioning of processor arrays
inferred← citeshttps://doi.org/10.1109/asap.1994.331800openalex-snapshot
On the injectivity of modular mappings
inferred← citeshttps://doi.org/10.1109/asap.1997.606830openalex-snapshot
Libraries of schedule-free operators in Alpha
inferred← citeshttps://doi.org/10.1109/cmpeur.1992.218413openalex-snapshot
Parallel architecture for a pel-recursive motion estimation algorithm
inferred← citeshttps://doi.org/10.1109/eurmic.1997.617337openalex-snapshot
Simulating systolic arrays on MasPar machines
inferred← citeshttps://doi.org/10.1109/iscas.1991.176006openalex-snapshot
Uniform design of parallel programs for DSP
inferred← citeshttps://doi.org/10.1109/iscas.1992.230160openalex-snapshot
The concepts of COMPAR- a compiler for massively parallel architectures
inferred← citeshttps://doi.org/10.1109/pmmp.1993.315551openalex-snapshot
An experimental parallelizing systolic compiler for regular programs
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641064openalex-snapshot
Cellular Broadcast In Regular Processor Arrays
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Hierarchical specification and transformation of algorithms and VLSI-architectures
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A Hardware–Software System for Tomographic Reconstruction
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Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology
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