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Structuring and automating hardware proofs in a higher-order theorem-proving environment

https://doi.org/10.1007/bf01383880
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/3-540-55179-4_35openalex-snapshot
Automating most parts of hardware proofs in HOL
inferredcites →https://doi.org/10.1007/3-540-55602-8_221openalex-snapshot
The FAUST — prover
inferredcites →https://doi.org/10.1007/978-1-4612-2360-3openalex-snapshot
First-Order Logic and Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0openalex-snapshot
Current Trends in Hardware Verification and Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0_1openalex-snapshot
Correctness Properties of the Viper Block Model: The Second Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot
VLSI Specification, Verification and Synthesis
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_1openalex-snapshot
Implementing Safety-Critical Systems: The VIPER Microprocessor
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot
HOL: A Proof Generating System for Higher-Order Logic
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_4openalex-snapshot
Formal Verification and Implementation of a Microprocessor
inferredcites →https://doi.org/10.1007/978-1-4684-0357-2openalex-snapshot
First-Order Logic and Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-3-322-90100-2openalex-snapshot
Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-3-322-90102-6openalex-snapshot
Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-94-011-1793-7_16openalex-snapshot
The Notion of Proof in Hardware Verification
inferredcites →https://doi.org/10.1007/bf00243000openalex-snapshot
The notion of proof in hardware verification
inferredcites →https://doi.org/10.1007/bf00244513openalex-snapshot
HARP: A tableau-based theorem prover
inferredcites →https://doi.org/10.1007/bf01201353openalex-snapshot
Untersuchungen �ber das logische Schlie�en. I
inferredcites →https://doi.org/10.1007/bf02432151openalex-snapshot
Seventy-five problems for testing automatic theorem provers
inferredcites →https://doi.org/10.1007/bfb0012847openalex-snapshot
SATCHMO: A theorem prover implemented in Prolog
inferredcites →https://doi.org/10.1016/0304-3975(81)90040-2openalex-snapshot
The undecidability of the second-order unification problem
inferredcites →https://doi.org/10.1016/0378-4754(89)90181-xopenalex-snapshot
A computational logic handbook
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50009-7openalex-snapshot
Efficient Representation and Computation of Tableaux Proofs
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50017-6openalex-snapshot
Modelling Generic Hardware Structures by Abstract Datatypes
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50018-8openalex-snapshot
A Methodology for Reusable Hardware Proofs
inferredcites →https://doi.org/10.1016/s0019-9958(73)90301-xopenalex-snapshot
The undecidability of unification in third order logic
inferredcites →https://doi.org/10.1016/s0736-5853(86)80087-9openalex-snapshot
Automated Reasoning: Introduction and Applications
inferredcites →https://doi.org/10.1049/ip-e.1986.0031openalex-snapshot
Specification and verification of digital systems using higher-order predicate logic
inferredcites →https://doi.org/10.1109/2.65openalex-snapshot
Formal verification of hardware correctness: introduction and survey of current research
inferredcites →https://doi.org/10.1109/dac.1985.1585981openalex-snapshot
A Model of Design Representation and Synthesis
inferredcites →https://doi.org/10.1109/dac.1988.14758openalex-snapshot
Formal specification and verification of hardware: a comparative case study
inferredcites →https://doi.org/10.1109/edac.1991.206349openalex-snapshot
Resolution-based correctness proofs of synchronous circuits
inferredcites →https://doi.org/10.1109/hol.1991.596284openalex-snapshot
Integrating A First-order Automatic prover In The HOL Environment
inferredcites →https://doi.org/10.1109/hol.1991.596286openalex-snapshot
First Steps Towards Automating Hardware Proofs In HOL
inferredcites →https://doi.org/10.1109/mc.1983.1654264openalex-snapshot
Guest Editors' Introduction: New VLSI Tools
inferredcites →https://doi.org/10.1109/test.1991.519494openalex-snapshot
A COMMON APPROACH TO TEST GENERATION AND HARDWARE VERIFICATION BASED ON TEMPORAL LOGIC
inferredcites →https://doi.org/10.1145/127601.127702openalex-snapshot
Representing circuits more efficiently in symbolic model checking
inferredcites →https://doi.org/10.1145/321250.321253openalex-snapshot
A Machine-Oriented Logic Based on the Resolution Principle
inferredcites →https://doi.org/10.2307/2269326openalex-snapshot
A note on the Entscheidungsproblem
inferredcites →https://doi.org/10.48456/tr-199openalex-snapshot
The HOL verification of ELLA designs
inferredcites →https://doi.org/10.5555/951513.951516openalex-snapshot
Resolution-based correctness proofs of synchronous circuits
inferredcites →https://doi.org/10.7146/dpb.v19i340.7648openalex-snapshot
Proceedings of the Third {HOL} Users Meeting: Aarhus University, 1-2 October 1990

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44464-5_13openalex-snapshot
Reflecting BDDs in Coq
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_21openalex-snapshot
Hierarchical Verification Using an MDG-HOL Hybrid Tool
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_128openalex-snapshot
A functional approach for formalizing regular hardware structures
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_137openalex-snapshot
Alternative proof procedures for finite-state machines in higher-order logic
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_142openalex-snapshot
Implementing a methodology for formally verifying RISC processors in HOL
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_150openalex-snapshot
Eliminating higher-order quantifiers to obtain decision procedures for hardware verification
inferred← citeshttps://doi.org/10.1007/3-540-58450-1_58openalex-snapshot
Implementational issues for verifying RISC-pipeline conflicts in HOL
inferred← citeshttps://doi.org/10.1007/3-540-59047-1_50openalex-snapshot
Effective theorem proving for hardware verification
inferred← citeshttps://doi.org/10.1007/3-540-59047-1_51openalex-snapshot
A formal framework for high level synthesis
inferred← citeshttps://doi.org/10.1007/3-540-59047-1_53openalex-snapshot
A tutorial on using PVS for hardware verification
inferred← citeshttps://doi.org/10.1007/3-540-60385-9_14openalex-snapshot
Formal support for the ELLA hardware description language
inferred← citeshttps://doi.org/10.1007/3-540-60385-9_9openalex-snapshot
State enumeration with abstract descriptions of state machines
inferred← citeshttps://doi.org/10.1007/978-3-642-78565-8_47openalex-snapshot
A Formalization of a Hierarchical Model for RISC Processors
inferred← citeshttps://doi.org/10.1007/978-94-017-0435-9_14openalex-snapshot
Cooperating Theorem Provers
inferred← citeshttps://doi.org/10.1007/bf00881952openalex-snapshot
Tableau-based theorem provers: Systems and implementations
inferred← citeshttps://doi.org/10.1007/bf01384237openalex-snapshot
Accelerating tableaux proofs using compact representations
inferred← citeshttps://doi.org/10.1007/bfb0021728openalex-snapshot
Embedding hardware verification within a commercial design framework
inferred← citeshttps://doi.org/10.1007/bfb0031809openalex-snapshot
A unified approach for combining different formalisms for hardware verification
inferred← citeshttps://doi.org/10.1007/s10009-002-0082-5openalex-snapshot
Hierarchical formal verification using a hybrid tool
inferred← citeshttps://doi.org/10.1016/b978-0-444-81641-2.50009-5openalex-snapshot
Hardware-Verification using First Order BDDs††This work has been partly financed by a German national grant, project Automated System Design, SFB No.358
inferred← citeshttps://doi.org/10.1023/a:1008622002590openalex-snapshot
A Practical Methodology for the Formal Verification of RISC Processors
inferred← citeshttps://doi.org/10.1093/comjnl/38.2.111openalex-snapshot
Formal specification and verification techniques for RISC pipeline conflicts
inferred← citeshttps://doi.org/10.1109/cmpass.1997.613200openalex-snapshot
Assured VLSI design with formal verification
inferred← citeshttps://doi.org/10.1109/edtc.1994.326809openalex-snapshot
Control path oriented verification of sequential generic circuits with control and data path
inferred← citeshttps://doi.org/10.1109/iccd.1993.393405openalex-snapshot
Towards a methodology for the formal hierarchical verification of RISC processors
inferred← citeshttps://doi.org/10.1109/iccd.1995.528795openalex-snapshot
Extending VLSI design with higher-order logic
inferred← citeshttps://doi.org/10.1109/icm.2001.997659openalex-snapshot
Automating the verification of parameterized hardware using a hybrid tool
inferred← citeshttps://doi.org/10.1109/ipdps.2001.925133openalex-snapshot
Proving properties of multidimensional recurrences with application to regular parallel algorithms
inferred← citeshttps://doi.org/10.1109/memcod.2012.6292302openalex-snapshot
Interactive verification of synchronous systems
inferred← citeshttps://doi.org/10.1109/pacrim.1995.519586openalex-snapshot
An analytical model for multi-group slotted ALOHA with capture
inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot
Formal verification in hardware design
inferred← citeshttps://doi.org/10.1524/itit.1999.41.2.12openalex-snapshot
Formale Verifikation eingebetteter Systeme
inferred← citeshttps://doi.org/10.22028/d291-25704openalex-snapshot
Formal verification of a fully IEEE compliant floating point unit
inferred← citeshttps://doi.org/10.3233/fi-1997-291207openalex-snapshot
MECHANIZATION OF REAL-TIME LINEAR CSP WITH HIGHER ORDER LOGIC
inferred← citeshttps://doi.org/10.5555/198174.198266openalex-snapshot
Formal verification of pipeline conflicts in RISC processors
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