On the public citation graph

The notion of proof in hardware verification

https://doi.org/10.1007/bf00243000
0 signed · 63 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/0-387-29831-2_7openalex-snapshot
Computers and the Sociology of Mathematical Proof
inferred← citeshttps://doi.org/10.1007/10930755_2openalex-snapshot
Formal Specification and Verification of ARM6
inferred← citeshttps://doi.org/10.1007/3-540-40891-6_19openalex-snapshot
Formal Methods Diffusion: Past Lessons and Future Prospects
inferred← citeshttps://doi.org/10.1007/3-540-48256-3_23openalex-snapshot
Symbolic Functional Evaluation
inferred← citeshttps://doi.org/10.1007/3-540-49366-2_1openalex-snapshot
Testing Proofs by Examples
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_126openalex-snapshot
Structure and behaviour in hardware verification
inferred← citeshttps://doi.org/10.1007/3-540-60043-4_71openalex-snapshot
A framework for machine-assisted user interface verification
inferred← citeshttps://doi.org/10.1007/978-1-4471-3558-6_12openalex-snapshot
Using Transformations and Verification in Circuit Design
inferred← citeshttps://doi.org/10.1007/978-1-4471-3558-6_13openalex-snapshot
Using LP to Study the Language PL 0 +
inferred← citeshttps://doi.org/10.1007/978-1-4471-3756-6_6openalex-snapshot
Formal Methods and the Sociology of Proof
inferred← citeshttps://doi.org/10.1007/978-3-540-30142-4_13openalex-snapshot
Proving Compatibility Using Refinement
inferred← citeshttps://doi.org/10.1007/978-3-540-39893-6_2openalex-snapshot
Model Based Code Verification
inferred← citeshttps://doi.org/10.1007/978-3-642-58622-4_9openalex-snapshot
Computers, Reasoning and Mathematical Practice
inferred← citeshttps://doi.org/10.1007/978-3-642-78565-8_47openalex-snapshot
A Formalization of a Hierarchical Model for RISC Processors
inferred← citeshttps://doi.org/10.1007/978-3-7091-7491-3_18openalex-snapshot
Validating Properties of Component-based Graphical User Interfaces
inferred← citeshttps://doi.org/10.1007/978-3-7091-9437-9_11openalex-snapshot
Combining Formal Techniques and Prototyping in User Interface Construction and Verification
inferred← citeshttps://doi.org/10.1007/978-94-010-0973-7_10openalex-snapshot
Philosophy and Computer Science
inferred← citeshttps://doi.org/10.1007/978-94-010-0973-7_11openalex-snapshot
Computer Reliability and Public Policy: Limits of Knowledge of Computer-Based Systems
inferred← citeshttps://doi.org/10.1007/978-94-011-1793-7_1openalex-snapshot
Computer Science and Philosophy
inferred← citeshttps://doi.org/10.1007/978-94-011-1793-7_18openalex-snapshot
Philosophical Aspects of Program Verification
inferred← citeshttps://doi.org/10.1007/bf00243132openalex-snapshot
Microprocessor design verification
inferred← citeshttps://doi.org/10.1007/bf00360581openalex-snapshot
Program verification, defeasible reasoning, and two views of computer science
inferred← citeshttps://doi.org/10.1007/bf00361037openalex-snapshot
Philosophical aspects of program verification
inferred← citeshttps://doi.org/10.1007/bf01383880openalex-snapshot
Structuring and automating hardware proofs in a higher-order theorem-proving environment
inferred← citeshttps://doi.org/10.1007/bf01383985openalex-snapshot
Deriving correctness properties of compiled code
inferred← citeshttps://doi.org/10.1007/bf01384073openalex-snapshot
Using transformations and verification in circuit design
inferred← citeshttps://doi.org/10.1007/bf01810294openalex-snapshot
Symbolic constraint handling through unification in finite algebras
inferred← citeshttps://doi.org/10.1007/bfb0013078openalex-snapshot
A programming logic for a verified structured assembly language
inferred← citeshttps://doi.org/10.1007/s10817-009-9144-7openalex-snapshot
Computer Assisted Reasoning
inferred← citeshttps://doi.org/10.1007/s11023-007-9060-8openalex-snapshot
Three Paradigms of Computer Science
inferred← citeshttps://doi.org/10.1016/0141-9331(93)90092-lopenalex-snapshot
The development of safe advanced road transport telematic software
inferred← citeshttps://doi.org/10.1016/0164-1212(94)00082-xopenalex-snapshot
The practice of formal methods in safety-critical systems
inferred← citeshttps://doi.org/10.1016/0951-8320(91)90047-bopenalex-snapshot
Formal methods in the production and assessment of safety critical software
inferred← citeshttps://doi.org/10.1016/b978-0-12-415040-9.50146-9openalex-snapshot
Safety-Critical Computing: Hazards, Practices, Standards, and Regulation
inferred← citeshttps://doi.org/10.1016/b978-0-444-89208-9.50019-3openalex-snapshot
Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50027-9openalex-snapshot
Deriving Correctness Properties of Compiled Code
inferred← citeshttps://doi.org/10.1016/b978-0-444-89901-9.50024-0openalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1016/s0304-3975(00)00350-9openalex-snapshot
Towards the animation of proofs – testing proofs by examples
inferred← citeshttps://doi.org/10.1017/s0265052500003538openalex-snapshot
Computer Reliability and Public Policy: Limits of Knowledge of Computer-Based Systems
inferred← citeshttps://doi.org/10.1023/a:1006262609127openalex-snapshot
A Mechanization of Unity in PC-NQTHM-92
inferred← citeshttps://doi.org/10.1023/a:1008622002590openalex-snapshot
A Practical Methodology for the Formal Verification of RISC Processors
inferred← citeshttps://doi.org/10.1023/a:1008643803725openalex-snapshot
Validation of HOL Proofs by Proof Checking
inferred← citeshttps://doi.org/10.1038/352467a0openalex-snapshot
The fangs of the VIPER
inferred← citeshttps://doi.org/10.1098/rsbm.2018.0019openalex-snapshot
Michael John Caldwell Gordon. 28 February 1948—22 August 2017
inferred← citeshttps://doi.org/10.1098/rsta.1992.0023openalex-snapshot
Will proof replace simulation?
inferred← citeshttps://doi.org/10.1098/rsta.2005.1649openalex-snapshot
Computing and the cultures of proving
inferred← citeshttps://doi.org/10.1109/12.805155openalex-snapshot
An application of formal analysis to software in a fault-tolerant environment
inferred← citeshttps://doi.org/10.1109/32.469458openalex-snapshot
Verifying a logic-synthesis algorithm and implementation: a case study in software verification
inferred← citeshttps://doi.org/10.1109/43.277609openalex-snapshot
Formal verification of sequential hardware: a tutorial
inferred← citeshttps://doi.org/10.1109/aspdac.1995.486385openalex-snapshot
Integrating design and verification environments through a logic supporting hardware diagrams
inferred← citeshttps://doi.org/10.1109/case.1995.465305openalex-snapshot
A framework for prototyping and mechanically verifying a class of user interfaces
inferred← citeshttps://doi.org/10.1109/cicc.1996.510579openalex-snapshot
A brief introduction to formal methods [hardware design]
inferred← citeshttps://doi.org/10.1109/cmpass.1991.161048openalex-snapshot
Report on the formal specification and partial verification of the VIPER microprocessor
inferred← citeshttps://doi.org/10.1109/cmpass.1993.288862openalex-snapshot
A tool for reasoning about software models
inferred← citeshttps://doi.org/10.1109/cmpass.1994.318453openalex-snapshot
Experiences formally verifying a network component
inferred← citeshttps://doi.org/10.1109/cmpcon.1991.128848openalex-snapshot
From formal verification to silicon compilation
inferred← citeshttps://doi.org/10.1109/hol.1991.596275openalex-snapshot
The Need For Formal Verification In Hardware Design And What Formal Verification Has Not Done For Me Lately
inferred← citeshttps://doi.org/10.1109/issre.1995.497644openalex-snapshot
The role of testing in the B formal development process
inferred← citeshttps://doi.org/10.1109/pacrim.1997.620351openalex-snapshot
Formal hardware verification with BDDs: an introduction
inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot
Formal verification in hardware design
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.3406/ahess.1998.279698openalex-snapshot
Histoire des techniques et sociologie de la connaissance
inferred← citeshttps://doi.org/10.7146/brics.v4i18.18945openalex-snapshot
How to Believe a Machine-Checked Proof
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.