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Verification of all circuits in a floating-point unit using word-level model checking
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-56922-7_14openalex-snapshot
Verification of a multiplier: 64 bits and beyond
inferredcites →https://doi.org/10.1007/3-540-59047-1_42openalex-snapshot
Non-restoring integer square root: A case study in design by principled optimization
inferredcites →https://doi.org/10.1007/bf01383955openalex-snapshot
A proof of the nonrestoring division algorithm and its implementation on an ALU
inferredcites →https://doi.org/10.1109/12.73590openalex-snapshot
On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication
inferredcites →https://doi.org/10.1109/40.46769openalex-snapshot
Developing the WTL3170/3171 Sparc floating-point coprocessors
inferredcites →https://doi.org/10.1109/arith.1985.6158929openalex-snapshot
The VLSI implementation of a square root algorithm
inferredcites →https://doi.org/10.1109/dac.1996.545657openalex-snapshot
Bit-level analysis of an SRT divider circuit
inferredcites →https://doi.org/10.1109/iccad.1993.580029openalex-snapshot
Dynamic variable ordering for ordered binary decision diagrams
inferredcites →https://doi.org/10.1109/iccad.1995.479995openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.1109/iccad.1995.480007openalex-snapshot
Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs
inferredcites →https://doi.org/10.1109/jrproc.1961.287780openalex-snapshot
Statistical Analysis of Certain Binary Division Algorithms
inferredcites →https://doi.org/10.1109/tc.1968.226439openalex-snapshot
Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
inferredcites →https://doi.org/10.1145/157485.164569openalex-snapshot
Spectral transforms for large boolean functions with applications to technology mapping
inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot
Verification of arithmetic circuits with binary moment diagrams
inferredcites →https://doi.org/10.1184/r1/6612938openalex-snapshot
Word Level Symbolic Model Checking A New Approach for Verifying Arithmetic Circuits
inferredcites →https://doi.org/10.21236/ada281028openalex-snapshot
Verification of Arithmetic Functions with Binary Moment Diagrams
inferredcites →https://doi.org/10.21236/ada294842openalex-snapshot
Bit-Level Analysis of an SRT Divider Circuit.
inferredcites →https://doi.org/10.21236/ada296684openalex-snapshot
Hybrid Decision Diagrams. Overcoming the Limitations of MTBDDs and BMDs,
inferredcites →https://doi.org/10.5555/224841.224863openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.5555/259794.259802openalex-snapshot
Dynamic variable ordering for ordered binary decision diagrams
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-44659-1_21openalex-snapshot
Divider Circuit Verification with Model Checking and Theorem Proving
inferred← citeshttps://doi.org/10.1007/3-540-45449-7_8openalex-snapshot
Verification of Embedded Software: Problems and Perspectives
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_23openalex-snapshot
Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study
inferred← citeshttps://doi.org/10.1007/3-540-63166-6_12openalex-snapshot
Automatic datapath extraction for efficient usage of HDD
inferred← citeshttps://doi.org/10.1007/978-0-387-35190-2_3openalex-snapshot
Verifying Out-of-Order Executions
inferred← citeshttps://doi.org/10.1007/978-3-030-68071-8_1openalex-snapshot
Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey
inferred← citeshttps://doi.org/10.1007/978-3-540-39724-3_7openalex-snapshot
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP
inferred← citeshttps://doi.org/10.1007/978-3-642-58322-3_24openalex-snapshot
Proving the Correctness of a Complete Microprocessor
inferred← citeshttps://doi.org/10.1007/bfb0028769openalex-snapshot
Verification of floating-point adders
inferred← citeshttps://doi.org/10.1007/bfb0055616openalex-snapshot
Herbrand automata for hardware verification
inferred← citeshttps://doi.org/10.1007/s10009-003-0120-yopenalex-snapshot
Properties of two’s complement floating point notations
inferred← citeshttps://doi.org/10.1007/s10009-006-0204-6openalex-snapshot
Putting it all together – Formal verification of the VAMP
inferred← citeshttps://doi.org/10.1007/s100090100037openalex-snapshot
Verification of arithmetic circuits using binary moment diagrams
inferred← citeshttps://doi.org/10.1007/s10703-005-1613-yopenalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1016/b978-155860798-9/50010-5openalex-snapshot
Floating-Point Representation, Algorithms, and Implementations
inferred← citeshttps://doi.org/10.1016/j.vlsi.2015.12.004openalex-snapshot
A dynamic specification to automatically debug and correct various divider circuits
inferred← citeshttps://doi.org/10.1016/s0167-9260(02)00047-0openalex-snapshot
Minimization of Word-Level Decision Diagrams
inferred← citeshttps://doi.org/10.1023/a:1008617612073openalex-snapshot
Modular Verification of SRT Division
inferred← citeshttps://doi.org/10.1109/43.969437openalex-snapshot
An efficient graph representation for arithmetic circuit verification
inferred← citeshttps://doi.org/10.1109/aspdac.2001.913299openalex-snapshot
Equivalence checking of integer multipliers
inferred← citeshttps://doi.org/10.1109/date.1999.761096openalex-snapshot
Formal verification of word-level specifications
inferred← citeshttps://doi.org/10.1109/dft.2014.6962068openalex-snapshot
Automated formal approach for debugging dividers using dynamic specification
inferred← citeshttps://doi.org/10.1109/iccad.1996.569822openalex-snapshot
ACV: an arithmetic circuit verifier
inferred← citeshttps://doi.org/10.1109/iccad.1997.643251openalex-snapshot
*PHDD: an efficient graph representation for floating point circuit verification
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323757openalex-snapshot
Efficient Formal Verification and Debugging of Arithmetic Divider Circuits
inferred← citeshttps://doi.org/10.1109/iccd.2000.878312openalex-snapshot
Efficient dynamic minimization of word-level DDs based on lower bound computation
inferred← citeshttps://doi.org/10.1109/icecs.2006.379845openalex-snapshot
Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification
inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot
Integrating Formal Verification into an Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.1109/test.2003.1270834openalex-snapshot
Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
inferred← citeshttps://doi.org/10.1145/288548.289082openalex-snapshot
Formal verification of pipeline control using controlled token nets and abstract interpretation
inferred← citeshttps://doi.org/10.1145/307418.307447openalex-snapshot
Formal verification of word-level specifications
inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot
Formal verification in hardware design
inferred← citeshttps://doi.org/10.1145/337292.337388openalex-snapshot
Formal verification of iterative algorithms in microprocessors
inferred← citeshttps://doi.org/10.1145/370155.370315openalex-snapshot
Equivalence checking of integer multipliers
inferred← citeshttps://doi.org/10.1145/972627.972633openalex-snapshot
Modeling and validation of pipeline specifications
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.23919/fmcad.2017.8102237openalex-snapshot
Column-wise verification of multipliers using computer algebra
inferred← citeshttps://doi.org/10.5555/244522.244833openalex-snapshot
ACV: an arithmetic circuit verifier
inferred← citeshttps://doi.org/10.5555/266388.266400openalex-snapshot
PHDD: an efficient graph representation for floating point circuit verification
inferred← citeshttps://doi.org/10.5555/368058.368313openalex-snapshot
Dynamic minimization of word-level decision diagrams
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