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An exercise in the automatic verification of asynchronous designs

https://doi.org/10.1007/bf01384047
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-55179-4_20openalex-snapshot
Generating BDDs for symbolic model checking in CCS
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0_1openalex-snapshot
Correctness Properties of the Viper Block Model: The Second Level
inferredcites →https://doi.org/10.1007/bf01178564openalex-snapshot
Receptive process theory
inferredcites →https://doi.org/10.1007/bfb0021722openalex-snapshot
Automatic verification of speed-independent circuit designs using the Circal system
inferredcites →https://doi.org/10.1007/bfb0023748openalex-snapshot
An algebra for delay-insensitive circuits
inferredcites →https://doi.org/10.1016/0304-3975(84)90113-0openalex-snapshot
Testing equivalences for processes
inferredcites →https://doi.org/10.1016/0378-4754(82)90066-0openalex-snapshot
Petri Net theory and the modeling of systems
inferredcites →https://doi.org/10.1016/0890-5401(90)90025-dopenalex-snapshot
CCS expressions, finite state processes, and three problems of equivalence
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/s0020-1383(70)80253-4openalex-snapshot
inferredcites →https://doi.org/10.1109/12.83619openalex-snapshot
The formal description and verification of hardware timing
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1109/tsmc.1973.4309232openalex-snapshot
Asynchronous Sequential Switching Circuits
inferredcites →https://doi.org/10.1145/3318.3322openalex-snapshot
CIRCAL and the representation of communication, concurrency, and time
inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot
Micropipelines
inferredcites →https://doi.org/10.1145/71317.1186643openalex-snapshot
The design of an asynchronous microprocessor
inferredcites →https://doi.org/10.21236/ada447033openalex-snapshot
Syntax-Directed Translation of Concurrent Programs into Self-Timed Circuits
inferredcites →https://doi.org/10.21236/ada447727openalex-snapshot
The Design of an Asynchronous Microprocessor
inferredcites →https://doi.org/10.5555/951513.951597openalex-snapshot
The VLSI-programming language Tangram and its translation into handshake circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-40922-x_16openalex-snapshot
A Methodology for the Formal Analysis of Asynchronous Micropipelines
inferred← citeshttps://doi.org/10.1007/3-540-45591-4_126openalex-snapshot
Compiling Process Algebraic Descriptions into Reconfigurable Logic
inferred← citeshttps://doi.org/10.1007/3-540-57091-8_41openalex-snapshot
A highly parallel FPGA-based machine and its formal verification
inferred← citeshttps://doi.org/10.1007/bfb0000466openalex-snapshot
Specification of timing constraints within the circal process algebra
inferred← citeshttps://doi.org/10.1007/bfb0000498openalex-snapshot
The circal system
inferred← citeshttps://doi.org/10.1007/bfb0014721openalex-snapshot
Modelling a time-dependent protocol using the Circal process algebra
inferred← citeshttps://doi.org/10.1007/s11334-005-0002-4openalex-snapshot
Property verification of asynchronous systems
inferred← citeshttps://doi.org/10.1016/j.micpro.2005.01.002openalex-snapshot
Programming paradigms for reconfigurable computing
inferred← citeshttps://doi.org/10.1016/j.scico.2008.09.011openalex-snapshot
On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
inferred← citeshttps://doi.org/10.1016/s0022-0000(03)00002-3openalex-snapshot
TTL: a modular language for hardware/software systems design
inferred← citeshttps://doi.org/10.1049/ip-cdt:20010579openalex-snapshot
Hardware compiler realising concurrent processes in reconfigurable logic
inferred← citeshttps://doi.org/10.1109/async.2007.19openalex-snapshot
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
inferred← citeshttps://doi.org/10.1109/csd.1998.657544openalex-snapshot
Integrating the verification of timing, performance and correctness properties of concurrent systems
inferred← citeshttps://doi.org/10.4204/eptcs.316.8openalex-snapshot
Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks
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