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An algebra for delay-insensitive circuits
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-15670-4_14openalex-snapshot
An improved failures model for communicating processes
inferredcites →https://doi.org/10.1007/3-540-51305-1_10openalex-snapshot
Networks of communicating processes and their (De-)composition
inferredcites →https://doi.org/10.1007/978-3-642-82921-5_4openalex-snapshot
Notes on Communicating Sequential Systems
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1016/0167-6423(89)90044-0openalex-snapshot
Algebraic theory of processes
inferredcites →https://doi.org/10.1016/0304-3975(88)90049-7openalex-snapshot
The laws of OCCAM programming
inferredcites →https://doi.org/10.1049/ip-e:19860034openalex-snapshot
Automatic verification of asynchronous circuits using temporal logic
inferredcites →https://doi.org/10.6100/ir25052openalex-snapshot
Classification and composition of delay-insensitive circuits
inferredcites →https://doi.org/10.6100/ir272918openalex-snapshot
Translating programs into delay-insensitive circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
inferredcites →https://doi.org/10.7907/zmy86-a1w29openalex-snapshot
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-36190-1_2openalex-snapshot
A Programming Approach to the Design of Asynchronous Logic Blocks
inferred← citeshttps://doi.org/10.1007/978-1-4471-3544-9_8openalex-snapshot
The Design of a Delay-Insensitive Stack
inferred← citeshttps://doi.org/10.1007/bf01384047openalex-snapshot
An exercise in the automatic verification of asynchronous designs
inferred← citeshttps://doi.org/10.1007/bfb0039070openalex-snapshot
Delay-insensitive circuits: An algebraic approach to their design
inferred← citeshttps://doi.org/10.1007/s11334-005-0002-4openalex-snapshot
Property verification of asynchronous systems
inferred← citeshttps://doi.org/10.1007/s11390-016-1613-yopenalex-snapshot
Modular Timing Constraints for Delay-Insensitive Systems
inferred← citeshttps://doi.org/10.1016/j.entcs.2005.04.014openalex-snapshot
Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware
inferred← citeshttps://doi.org/10.1016/j.entcs.2005.05.042openalex-snapshot
Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs
inferred← citeshttps://doi.org/10.1016/j.tcs.2017.11.027openalex-snapshot
Quantum structures in qudit spaces
inferred← citeshttps://doi.org/10.1016/s0304-3975(99)00273-xopenalex-snapshot
Delay-insensitivity and ternary simulation
inferred← citeshttps://doi.org/10.1109/43.329261openalex-snapshot
A correctness criterion for asynchronous circuit validation and optimization
inferred← citeshttps://doi.org/10.1109/async.1994.656312openalex-snapshot
Efficient building blocks for delay insensitive circuits
inferred← citeshttps://doi.org/10.1109/async.1996.494453openalex-snapshot
Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits
inferred← citeshttps://doi.org/10.1109/async.1997.587173openalex-snapshot
Using metrics for proof rules for recursively defined delay-insensitive specifications
inferred← citeshttps://doi.org/10.1109/async.2002.1000303openalex-snapshot
Asynchronous circuit synthesis by direct mapping: interfacing to environment
inferred← citeshttps://doi.org/10.1109/glsv.1994.289972openalex-snapshot
Basic building blocks for asynchronous packet routers
inferred← citeshttps://doi.org/10.1109/iccd.1992.276267openalex-snapshot
Delay models for verifying speed-dependent asynchronous circuits
inferred← citeshttps://doi.org/10.1145/343647.343725openalex-snapshot
Delay-insensitive interface specification and synthesis
inferred← citeshttps://doi.org/10.15760/etd.2635openalex-snapshot
Formal Modeling and Verification of Delay-Insensitive Circuits
inferred← citeshttps://doi.org/10.21236/ada256199openalex-snapshot
Trace Algebra for Automatic Verification of Real-Time Concurrent Systems
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