On the public citation graph
Synchronization barrier and related tools for shared memory parallel programming
0 signed · 45 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf00289237openalex-snapshot
An approach to automating the verification of compact parallel coordination programs. I
inferredcites →https://doi.org/10.1007/bf01379320openalex-snapshot
Two algorithms for barrier synchronization
inferredcites →https://doi.org/10.1145/42190.42278openalex-snapshot
Simple, efficient, asynchronous parallel algorithms for maximization
inferredcites →https://doi.org/10.1145/63238.63247openalex-snapshot
Efficient distributed event-driven simulations of multiple-loop networks
inferredcites →https://doi.org/10.1145/69624.357206openalex-snapshot
Basic Techniques for the Efficient Coordination of Very Large Numbers of Cooperating Sequential Processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.6241openalex-snapshot
Reducing the burden of parallel loop schedulers for many‐core processors
inferred← citeshttps://doi.org/10.1006/jpdc.1995.1035openalex-snapshot
Static Barrier MIMD: Architecture and Performance Analysis
inferred← citeshttps://doi.org/10.1006/jpdc.1996.1273openalex-snapshot
Low-Cost, High-Performance Barrier Synchronization on Networks of Workstations
inferred← citeshttps://doi.org/10.1007/3-540-53065-7_136openalex-snapshot
Scalable cache coherence for large shared memory multiprocessors
inferred← citeshttps://doi.org/10.1007/3-540-55437-8_67openalex-snapshot
Scalable cache coherence for shared memory multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-030-85262-7_2openalex-snapshot
Vectorized Barrier and Reduction in LLVM OpenMP Runtime
inferred← citeshttps://doi.org/10.1007/978-3-031-01740-7openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.1007/978-3-031-85697-6_18openalex-snapshot
Flexible Algorithms for Persistent MPI Allreduce Communication
inferred← citeshttps://doi.org/10.1007/bf02577741openalex-snapshot
Fast, contention-free combining tree barriers for shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1007/s10817-013-9290-9openalex-snapshot
On Automation in the Verification of Software Barriers: Experience Report
inferred← citeshttps://doi.org/10.1016/j.future.2012.03.018openalex-snapshot
Direct approaches to exploit many-core architecture in bioinformatics
inferred← citeshttps://doi.org/10.1016/s0065-2458(00)80004-2openalex-snapshot
Shared memory and distributed shared memory systems: A survey
inferred← citeshttps://doi.org/10.1023/a:1013153020460openalex-snapshot
Two-Phase Barrier: A Synchronization Primitive for Improving the Processor Utilization
inferred← citeshttps://doi.org/10.1109/71.406967openalex-snapshot
Performance of barrier synchronization methods in a multiaccess network
inferred← citeshttps://doi.org/10.1109/cicc.2010.5617394openalex-snapshot
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor
inferred← citeshttps://doi.org/10.1109/csf.2016.29openalex-snapshot
Automated Reasoning for Equivalences in the Applied Pi Calculus with Barriers
inferred← citeshttps://doi.org/10.1109/hipc.1996.565849openalex-snapshot
A distributed barrier synchronization solution in hardware for 2D-mesh multicomputers
inferred← citeshttps://doi.org/10.1109/hpcsim.2013.6641445openalex-snapshot
One-sided communication and synchronization for non-coherent memory-coupled cores
inferred← citeshttps://doi.org/10.1109/icci.1993.315383openalex-snapshot
Performance of barrier synchronization methods in a multi-access network
inferred← citeshttps://doi.org/10.1109/icebe.2008.13openalex-snapshot
Performance Implications of Next-Generation Multi-processing Platforms on e-Business Server Applications
inferred← citeshttps://doi.org/10.1109/icpads.2002.1183406openalex-snapshot
Evaluating the speedup of a MPI-based distributed dispersion simulator for groundwater systems
inferred← citeshttps://doi.org/10.1109/icpp.1994.23openalex-snapshot
A Distributed Hardware Mechanism for Process Synchronization on Shared-Bus Multiprocessors
inferred← citeshttps://doi.org/10.1109/icppw.2002.1039746openalex-snapshot
An evaluation of the speedup of a preliminary distributed MPI-implementation for groundwater simulation dispersion system
inferred← citeshttps://doi.org/10.1109/inss.2010.5573561openalex-snapshot
A relaxed synchronization primitive for macroprogramming systems
inferred← citeshttps://doi.org/10.1109/ipdps.2010.5470477openalex-snapshot
Inter-block GPU communication via fast barrier synchronization
inferred← citeshttps://doi.org/10.1109/ipdpsw.2018.00124openalex-snapshot
Barrier Synchronization: Simplified, Generalized, and Solved Without Mutual Exclusion
inferred← citeshttps://doi.org/10.1109/ipps.1993.262852openalex-snapshot
Linked list cache coherence for scalable shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/spdp.1990.143520openalex-snapshot
Barrier synchronization over multistage interconnection networks
inferred← citeshttps://doi.org/10.1145/103727.103729openalex-snapshot
Algorithms for scalable synchronization on shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/106972.106999openalex-snapshot
Synchronization without contention
inferred← citeshttps://doi.org/10.1145/140901.140923openalex-snapshot
Subset barrier synchronization on a private-memory parallel system
inferred← citeshttps://doi.org/10.1145/1620405.1620416openalex-snapshot
Avoiding unbounded priority inversion in barrier protocols using gang priority management
inferred← citeshttps://doi.org/10.1145/237578.237610openalex-snapshot
Synchronization hardware for networks of workstations
inferred← citeshttps://doi.org/10.1145/244764.244765openalex-snapshot
Scheduler-conscious synchronization
inferred← citeshttps://doi.org/10.1177/10943420251363423openalex-snapshot
A compilation-based approach to performant reduction and redistribution collective communication algorithms
inferred← citeshttps://doi.org/10.21236/ad1000607openalex-snapshot
Runtime Systems for Extreme Scale Platforms
inferred← citeshttps://doi.org/10.2200/s00499ed1v01y201304cac023openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.3233/jcs-171013openalex-snapshot
Automated reasoning for equivalences in the applied pi calculus with barriers
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.