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Fast, contention-free combining tree barriers for shared-memory multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01379320openalex-snapshot
Two algorithms for barrier synchronization
inferredcites →https://doi.org/10.1007/bf01407897openalex-snapshot
A scalable implementation of barrier synchronization using an adaptive combining tree
inferredcites →https://doi.org/10.1007/bf01407956openalex-snapshot
Synchronization barrier and related tools for shared memory parallel programming
inferredcites →https://doi.org/10.1016/0022-0000(86)90021-8openalex-snapshot
Concurrent operations on B∗-trees with overtaking
inferredcites →https://doi.org/10.1109/2.55501openalex-snapshot
Synchronization algorithms for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/71.80120openalex-snapshot
The performance of spin lock alternatives for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/ipps.1992.222989openalex-snapshot
Scalable reader-writer locks for parallel systems
inferredcites →https://doi.org/10.1109/spdp.1990.143520openalex-snapshot
Barrier synchronization over multistage interconnection networks
inferredcites →https://doi.org/10.1109/tc.1987.1676921openalex-snapshot
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
inferredcites →https://doi.org/10.1145/103727.103729openalex-snapshot
Algorithms for scalable synchronization on shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/106972.106999openalex-snapshot
Synchronization without contention
inferredcites →https://doi.org/10.1145/106974.106999openalex-snapshot
Synchronization without contention
inferredcites →https://doi.org/10.1145/109625.109637openalex-snapshot
Scalable reader-writer synchronization for shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/298514.298580openalex-snapshot
A framework for the performance analysis of concurrent B-tree algorithms
inferredcites →https://doi.org/10.1145/319628.319663openalex-snapshot
Efficient locking for concurrent operations on B-trees
inferredcites →https://doi.org/10.1145/68182.68187openalex-snapshot
The fuzzy barrier: a mechanism for high speed synchronization of processors
inferredcites →https://doi.org/10.1145/70082.68187openalex-snapshot
The fuzzy barrier: a mechanism for high speed synchronization of processors
inferredcites →https://doi.org/10.21236/ada243147openalex-snapshot
Scalable Reader-Writer Locks for Parallel Systems
inferredcites →https://doi.org/10.2172/10142365openalex-snapshot
Kendall Square multiprocessor: Early experiences and performance
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.5527openalex-snapshot
A barrier optimization framework for NUMA multi‐core system
inferred← citeshttps://doi.org/10.1007/978-3-031-01740-7openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.1007/978-3-642-40698-0_8openalex-snapshot
An OpenMP* Barrier Using SIMD Instructions for Intel® Xeon PhiTM Coprocessor
inferred← citeshttps://doi.org/10.1007/s10817-013-9290-9openalex-snapshot
On Automation in the Verification of Software Barriers: Experience Report
inferred← citeshttps://doi.org/10.1016/j.future.2015.04.005openalex-snapshot
Time Donating Barrier for efficient task scheduling in competitive multicore systems
inferred← citeshttps://doi.org/10.1016/j.jpdc.2005.04.013openalex-snapshot
Fast synchronization on shared-memory multiprocessors: An architectural approach
inferred← citeshttps://doi.org/10.1016/j.procs.2021.04.208openalex-snapshot
Adaptive MPI collective operations based on evaluations in LogP model
inferred← citeshttps://doi.org/10.1016/s0167-8191(01)00123-5openalex-snapshot
Implementation and evaluation of directory hints in CC-NUMA multiprocessors
inferred← citeshttps://doi.org/10.1023/a:1008115125409openalex-snapshot
Exploiting Network Locality for CC-NUMA Multiprocessors
inferred← citeshttps://doi.org/10.1023/a:1008161716113openalex-snapshot
An Application-Driven Study of Multicast Communication for Write Invalidation
inferred← citeshttps://doi.org/10.1023/a:1013153020460openalex-snapshot
Two-Phase Barrier: A Synchronization Primitive for Improving the Processor Utilization
inferred← citeshttps://doi.org/10.1109/csci54926.2021.00334openalex-snapshot
Non-Blocking Technique for Parallel Algorithms with Global Barrier Synchronization
inferred← citeshttps://doi.org/10.1109/fareastcon.2018.8602527openalex-snapshot
Adaptive Barrier Algorithm in MPI Based on Analytical Evaluations for Communication Time in the LogP Model of Parallel Computation
inferred← citeshttps://doi.org/10.1109/fpl.2009.5272560openalex-snapshot
Hardware implementation of MPI_Barrier on an FPGA cluster
inferred← citeshttps://doi.org/10.1109/hipc.2015.51openalex-snapshot
Efficient Barrier Implementation on the POWER8 Processor
inferred← citeshttps://doi.org/10.1109/hpcc.2010.30openalex-snapshot
Insertion Tree Phasers: Efficient and Scalable Barrier Synchronization for Fine-Grained Parallelism
inferred← citeshttps://doi.org/10.1109/icdcs.2000.840976openalex-snapshot
Boosting the performance of NOW-based shared memory multiprocessors through directory hints
inferred← citeshttps://doi.org/10.1109/icpp.2000.876166openalex-snapshot
The thread-based protocol engines for CC-NUMA multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.2005.39openalex-snapshot
Fast Barriers for Scalable ccNUMA Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2004.1302981openalex-snapshot
Highly efficient synchronization based on active memory operations
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639561openalex-snapshot
Fast barrier synchronization for InfiniBand/spl trade/
inferred← citeshttps://doi.org/10.1109/ipdps.2010.5470414openalex-snapshot
Hierarchical phasers for scalable synchronization and reductions in dynamic parallelism
inferred← citeshttps://doi.org/10.1109/pdgc.2014.7030721openalex-snapshot
Optimizing MPI collectives on intel MIC through effective use of cache
inferred← citeshttps://doi.org/10.1109/simsym.2000.844930openalex-snapshot
MICA: a memory and interconnect simulation environment for cache-based architectures
inferred← citeshttps://doi.org/10.1109/tc.2010.15openalex-snapshot
Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes
inferred← citeshttps://doi.org/10.1145/1362622.1362692openalex-snapshot
Implementation and performance analysis of non-blocking collective operations for MPI
inferred← citeshttps://doi.org/10.1145/1950413.1950445openalex-snapshot
Scalable and deterministic timing-driven parallel placement for FPGAs
inferred← citeshttps://doi.org/10.1145/2370816.2370856openalex-snapshot
Runtime detection and optimization of collective communication patterns
inferred← citeshttps://doi.org/10.1145/244764.244765openalex-snapshot
Scheduler-conscious synchronization
inferred← citeshttps://doi.org/10.1145/3727639openalex-snapshot
Unleashing Parallelism with Elastic-Barriers
inferred← citeshttps://doi.org/10.1504/ijhpcn.2004.007563openalex-snapshot
Scalable barrier synchronisation for large-scale shared-memory multiprocessors
inferred← citeshttps://doi.org/10.18130/v3zr90openalex-snapshot
Addressing Processor Over-Provisioning on Large-Scale Multi-Core Platforms
inferred← citeshttps://doi.org/10.21236/ad1000607openalex-snapshot
Runtime Systems for Extreme Scale Platforms
inferred← citeshttps://doi.org/10.2200/s00499ed1v01y201304cac023openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.3724/sp.j.1016.2008.01727openalex-snapshot
Design of Barrier Network of Dawning 5000 High Performance Computer
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96011openalex-snapshot
SIMD@OpenMP : a programming model approach to leverage SIMD features
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