On the public citation graph
Scalable cache consistency for hierarchically structured multiprocessors
0 signed · 33 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.144442openalex-snapshot
From paper to office document standard representation
inferredcites →https://doi.org/10.1109/2.55500openalex-snapshot
Directory-based cache coherence in large-scale multiprocessors
inferredcites →https://doi.org/10.1109/2.67196openalex-snapshot
Hector: a hierarchically structured shared-memory multiprocessor
inferredcites →https://doi.org/10.1109/40.124376openalex-snapshot
The Scalable Coherent Interface and related standards projects
inferredcites →https://doi.org/10.1109/cmpcon.1988.4913openalex-snapshot
The 4D-MP graphics superworkstation: computing+graphics=40 MIPS+MFLOPS and 100000 lighted polygons per second
inferredcites →https://doi.org/10.1109/mascot.1994.284422openalex-snapshot
MINT: a front end for efficient simulation of shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1145/115952.115964openalex-snapshot
Race-free interconnection networks and multiprocessor consistency
inferredcites →https://doi.org/10.1145/17356.17406openalex-snapshot
Memory access buffering in multiprocessors
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/325096.325132openalex-snapshot
The directory-based cache coherence protocol for the DASH multiprocessor
inferredcites →https://doi.org/10.21236/ada237629openalex-snapshot
LimitLESS Directories: A Scalable Cache Coherence Scheme
inferredcites →https://doi.org/10.25549/usctheses-c17-774010openalex-snapshot
Access ordering and coherence in shared memory multiprocessors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.heliyon.2023.e20064openalex-snapshot
Self-complexification through integral feedback in eusocial paper wasps of various levels of sociality
inferred← citeshttps://doi.org/10.1016/j.parco.2006.10.001openalex-snapshot
Torus Ring: improving performance of interconnection network by modifying hierarchical ring
inferred← citeshttps://doi.org/10.1016/s0045-7906(00)00044-6openalex-snapshot
A comparative study of bidirectional ring and crossbar interconnection networks
inferred← citeshttps://doi.org/10.1109/12.902749openalex-snapshot
Hierarchical ring network configuration and performance modeling
inferred← citeshttps://doi.org/10.1109/hpca.1997.569606openalex-snapshot
A performance comparison of hierarchical ring- and mesh-connected multiprocessor networks
inferred← citeshttps://doi.org/10.1109/icpp.1997.622653openalex-snapshot
Performance and configuration of hierarchical ring networks for multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.2000.876165openalex-snapshot
The NUMAchine multiprocessor
inferred← citeshttps://doi.org/10.1109/icpp.2010.52openalex-snapshot
Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isca.2003.1206999openalex-snapshot
Token Coherence: decoupling performance and correctness
inferred← citeshttps://doi.org/10.1109/micro.2006.14openalex-snapshot
Coherence Ordering for Ring-based Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/mixdes.2014.6872145openalex-snapshot
A brief overview of the challenges of the multicore roadmap
inferred← citeshttps://doi.org/10.1109/tc.2021.3089044openalex-snapshot
Scalability in Computing and Robotics
inferred← citeshttps://doi.org/10.1145/277044.277057openalex-snapshot
Design and implementation of the NUMAchine multiprocessor
inferred← citeshttps://doi.org/10.15760/etd.5858openalex-snapshot
Enhancements to the scalable coherent interface cache protocol
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.