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Coherence Ordering for Ring-based Chip Multiprocessors

https://doi.org/10.1109/micro.2006.14

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot

SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance

inferredcites →https://doi.org/10.1007/bf01901614openalex-snapshot

Scalable cache consistency for hierarchically structured multiprocessors

inferredcites →https://doi.org/10.1109/12.256449openalex-snapshot

Cache invalidation patterns in shared-memory multiprocessors

inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot

Simics: A full system simulation platform

inferredcites →https://doi.org/10.1109/40.124376openalex-snapshot

The Scalable Coherent Interface and related standards projects

inferredcites →https://doi.org/10.1109/40.653032openalex-snapshot

Starfire: extending the SMP envelope

inferredcites →https://doi.org/10.1109/40.988687openalex-snapshot

The Alpha 21364 network architecture

inferredcites →https://doi.org/10.1109/5.920580openalex-snapshot

The future of wires

inferredcites →https://doi.org/10.1109/async.2003.1199174openalex-snapshot

Self-timed ring for globally-asynchronous locally-synchronous systems

inferredcites →https://doi.org/10.1109/his.2001.946702openalex-snapshot

The Alpha 21364 network architecture

inferredcites →https://doi.org/10.1109/hpca.2003.1183520openalex-snapshot

Variability in architectural simulations of multi-threaded workloads

inferredcites →https://doi.org/10.1109/hpca.2005.17openalex-snapshot

Improving Multiple-CMP Systems Using Token Coherence

inferredcites →https://doi.org/10.1109/icpads.1998.741012openalex-snapshot

PANDA: ring-based multiprocessor system using new snooping protocol

inferredcites →https://doi.org/10.1109/isca.1990.134520openalex-snapshot

The directory-based cache coherence protocol for the DASH multiprocessor

inferredcites →https://doi.org/10.1109/isca.1993.698567openalex-snapshot

The Performance Of Cache-coherent Ring-based Multiprocessors

inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot

Piranha: a scalable architecture based on single-chip multiprocessing

inferredcites →https://doi.org/10.1109/micro.2005.37openalex-snapshot

/spl mu/Complexity: estimating processor design effort

inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot

The AMD opteron processor for multiprocessor servers

inferredcites →https://doi.org/10.1109/mm.2006.73openalex-snapshot

IPC Considered Harmful for Multiprocessor Workloads

inferredcites →https://doi.org/10.1109/pact.2001.953300openalex-snapshot

Exploring the design space of future CMPs

inferredcites →https://doi.org/10.1109/tpds.2002.1011412openalex-snapshot

Specifying and verifying a broadcast and a multicast snooping cache coherence protocol

inferredcites →https://doi.org/10.1145/1080695.1070004openalex-snapshot

Interconnections in Multi-Core Architectures

inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot

Cooperative Caching for Chip Multiprocessors

inferredcites →https://doi.org/10.1145/1150019.1136514openalex-snapshot

Flexible Snooping

inferredcites →https://doi.org/10.1145/165123.165162openalex-snapshot

The performance of cache-coherent ring-based multiprocessors

inferredcites →https://doi.org/10.1145/232973.233006openalex-snapshot

STiNG

inferredcites →https://doi.org/10.1145/264107.264206openalex-snapshot

The SGI Origin

inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot

Lockup-free instruction fetch/prefetch cache organization

inferredcites →https://doi.org/10.1145/325096.325132openalex-snapshot

The directory-based cache coherence protocol for the DASH multiprocessor

inferredcites →https://doi.org/10.1145/339647.339696openalex-snapshot

Piranha

inferredcites →https://doi.org/10.1145/356989.356991openalex-snapshot

Architecture and design of AlphaServer GS320

inferredcites →https://doi.org/10.1145/357980.358015openalex-snapshot

Ethernet

inferredcites →https://doi.org/10.1145/360248.360253openalex-snapshot

Ethernet

inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot

Route packets, net wires

inferredcites →https://doi.org/10.1145/378993.378997openalex-snapshot

Architecture and design of AlphaServer GS320

inferredcites →https://doi.org/10.1145/511334.511349openalex-snapshot

Full-system timing-first simulation

inferredcites →https://doi.org/10.1145/511348.511349openalex-snapshot

Full-system timing-first simulation

inferredcites →https://doi.org/10.1145/800017.800516openalex-snapshot

Temporal verification of carrier-sense local area network protocols

inferredcites →https://doi.org/10.1145/859618.859640openalex-snapshot

Token coherence

inferredcites →https://doi.org/10.1145/859618.859642openalex-snapshot

Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors

inferredcites →https://doi.org/10.1145/861.871openalex-snapshot

Local networks

inferredcites →https://doi.org/10.1147/rd.461.0005openalex-snapshot

POWER4 system microarchitecture

inferredcites →https://doi.org/10.1147/rd.494.0505openalex-snapshot

POWER5 system microarchitecture

inferredcites →https://doi.org/10.1147/rd.515.0545openalex-snapshot

Cell Broadband Engine processor: Design and implementation

inferredcites →https://doi.org/10.5555/645988.674164openalex-snapshot

Exploring the Design Space of Future CMPs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-01733-9_7openalex-snapshot

Snooping Coherence Protocols

inferred← citeshttps://doi.org/10.1007/978-3-031-01764-3_7openalex-snapshot

Snooping Coherence Protocols

inferred← citeshttps://doi.org/10.1007/s11432-023-3926-8openalex-snapshot

Review of chiplet-based design: system architecture and interconnection

inferred← citeshttps://doi.org/10.1109/fccm.2014.43openalex-snapshot

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

inferred← citeshttps://doi.org/10.1109/hoti.2011.11openalex-snapshot

Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems

inferred← citeshttps://doi.org/10.1109/hpca.2007.346210openalex-snapshot

An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing

inferred← citeshttps://doi.org/10.1109/hpca.2009.4798238openalex-snapshot

In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects

inferred← citeshttps://doi.org/10.1109/hpcsim.2009.5192668openalex-snapshot

RING-DATA ORDER: A new cache coherence protocol for ring-based multicores

inferred← citeshttps://doi.org/10.1109/iceeot.2016.7755093openalex-snapshot

Cache coherence: A walkthrough of mechanisms and challenges

inferred← citeshttps://doi.org/10.1109/icpads.2009.32openalex-snapshot

Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP

inferred← citeshttps://doi.org/10.1109/micro.2007.37openalex-snapshot

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors

inferred← citeshttps://doi.org/10.1109/micro.2007.43openalex-snapshot

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

inferred← citeshttps://doi.org/10.1109/micro.2008.4771777openalex-snapshot

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence

inferred← citeshttps://doi.org/10.1109/micro.2008.4771778openalex-snapshot

Token tenure: PATCHing token counting using directory-based cache coherence

inferred← citeshttps://doi.org/10.1109/mm.2008.19openalex-snapshot

Virtual Hierarchies

inferred← citeshttps://doi.org/10.1109/newcas.2007.4488016openalex-snapshot

A single-chip ring-based multiprocessor with region-level filtering of coherence traffic

inferred← citeshttps://doi.org/10.1109/nocs.2010.22openalex-snapshot

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

inferred← citeshttps://doi.org/10.1109/pact.2013.6618827openalex-snapshot

Automatic OpenCL work-group size selection for multicore CPUs

inferred← citeshttps://doi.org/10.1109/pdp50117.2020.00026openalex-snapshot

RSMCC: Enabling Ring-based Software Managed Cache-Coherent Embedded SoCs

inferred← citeshttps://doi.org/10.1109/sasp.2009.5226329openalex-snapshot

Workload adaptive shared memory multicore processors with reconfigurable interconnects

inferred← citeshttps://doi.org/10.1109/sc.2008.5215354openalex-snapshot

Extending CC-NUMA systems to support write update optimizations

inferred← citeshttps://doi.org/10.1109/tpds.2011.80openalex-snapshot

Efficient and Scalable Starvation Prevention Mechanism for Token Coherence

inferred← citeshttps://doi.org/10.1145/1150019.1136509openalex-snapshot

Cooperative Caching for Chip Multiprocessors

inferred← citeshttps://doi.org/10.1145/1250662.1250670openalex-snapshot

Virtual hierarchies to support server consolidation

inferred← citeshttps://doi.org/10.1145/1273440.1250670openalex-snapshot

Virtual hierarchies to support server consolidation

inferred← citeshttps://doi.org/10.1145/1378533.1378536openalex-snapshot

A consistency architecture for hierarchical shared caches

inferred← citeshttps://doi.org/10.1145/1454115.1454137openalex-snapshot

Scalable and reliable communication for hardware transactional memory

inferred← citeshttps://doi.org/10.1145/1721650.1721653openalex-snapshot

Routing in self-organizing nano-scale irregular networks

inferred← citeshttps://doi.org/10.1145/1839667.1839668openalex-snapshot

Token tenure and PATCH

inferred← citeshttps://doi.org/10.1145/1854273.1854292openalex-snapshot

Subspace snooping

inferred← citeshttps://doi.org/10.1145/1973009.1973019openalex-snapshot

Run-time energy management of manycore systems through reconfigurable interconnects

inferred← citeshttps://doi.org/10.1145/2212908.2212929openalex-snapshot

Improving coherence protocol reactiveness by trading bandwidth for latency

inferred← citeshttps://doi.org/10.1145/2228360.2228511openalex-snapshot

A hybrid NoC design for cache coherence optimization for chip multiprocessors

inferred← citeshttps://doi.org/10.1145/2682583openalex-snapshot

Learning your limit

inferred← citeshttps://doi.org/10.1145/3061639.3062278openalex-snapshot

Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems

inferred← citeshttps://doi.org/10.1145/3392717.3392735openalex-snapshot

SB-Fetch

inferred← citeshttps://doi.org/10.1155/2010/205852openalex-snapshot

A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

inferred← citeshttps://doi.org/10.14288/1.0166749openalex-snapshot

Locality and scheduling in the massively multithreaded era

inferred← citeshttps://doi.org/10.2200/s00346ed1v01y201104cac016openalex-snapshot

A Primer on Memory Consistency and Cache Coherence

inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot

On-Chip Networks, Second Edition

inferred← citeshttps://doi.org/10.2200/s00962ed2v01y201910cac049openalex-snapshot

A Primer on Memory Consistency and Cache Coherence, Second Edition

inferred← citeshttps://doi.org/10.4995/thesis/10251/6024openalex-snapshot

Efficient techniques to provide scalability for token-based cache coherence protocols.

inferred← citeshttps://doi.org/10.5821/dissertation-2117-94918openalex-snapshot

Automatic synthesis and optimization of chip multiprocessors

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