On the public citation graph

Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution

https://doi.org/10.1007/bf03356749
0 signed · 47 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/isca.1990.134545openalex-snapshot
Boosting beyond static scheduling in a superscalar processor
inferredcites →https://doi.org/10.1109/isca.1994.288156openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1109/mc.1984.1658927openalex-snapshot
Branch Prediction Strategies and Branch Target Buffer Design
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1994.717461openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1109/t-c.1972.223514openalex-snapshot
The Inhibition of Potential Parallelism by Conditional Jumps
inferredcites →https://doi.org/10.1145/115952.115979openalex-snapshot
IMPACT
inferredcites →https://doi.org/10.1145/115952.115981openalex-snapshot
Exploiting fine-grained parallelism through a combination of hardware and software techniques
inferredcites →https://doi.org/10.1145/123465.123475openalex-snapshot
Two-level adaptive training branch prediction
inferredcites →https://doi.org/10.1145/139669.139709openalex-snapshot
Alternative implementations of two-level adaptive branch prediction
inferredcites →https://doi.org/10.1145/143095.143146openalex-snapshot
Eliminating branches using a superoptimizer and the GNU C compiler
inferredcites →https://doi.org/10.1145/143103.143146openalex-snapshot
Eliminating branches using a superoptimizer and the GNU C compiler
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/18906.18916openalex-snapshot
HPS, a new microarchitecture: rationale and introduction
inferredcites →https://doi.org/10.1145/18906.18917openalex-snapshot
Critical issues regarding HPS, a high performance microarchitecture
inferredcites →https://doi.org/10.1145/191995.192022openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1145/192724.192727openalex-snapshot
Branch classification
inferredcites →https://doi.org/10.1145/192724.192753openalex-snapshot
The effects of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/192724.192755openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/192724.197407openalex-snapshot
Facilitating superscalar processing via a combined static/dynamic register renaming scheme
inferredcites →https://doi.org/10.1145/325096.325160openalex-snapshot
Boosting beyond static scheduling in a superscalar processor
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1145/70082.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
inferredcites →https://doi.org/10.5555/110382.110438openalex-snapshot
Parallelization of loops with exits on pipelined architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11573937_10openalex-snapshot
RIMP: Runtime Implicit Predication
inferred← citeshttps://doi.org/10.1016/s0141-9331(02)00023-6openalex-snapshot
Evaluation of dynamic branch predictors for modern ILP processors
inferred← citeshttps://doi.org/10.1080/01495739708941414openalex-snapshot
PARALLELISING COMPILERS AND SYSTEMS
inferred← citeshttps://doi.org/10.1109/cgo.2006.1openalex-snapshot
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set
inferred← citeshttps://doi.org/10.1109/cgo.2007.31openalex-snapshot
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
inferred← citeshttps://doi.org/10.1109/hpca.2007.346186openalex-snapshot
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00019openalex-snapshot
Auto-Predication of Critical Branches
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00091openalex-snapshot
Alternate Path Fetch
inferred← citeshttps://doi.org/10.1109/iwia.1999.898839openalex-snapshot
Selective guarded execution using profiling on a dynamically scheduled processor
inferred← citeshttps://doi.org/10.1109/micro.2001.991117openalex-snapshot
The impact of If-conversion and branch prediction on program execution on the Intel/sup R/ Itanium/sup TM/ processor
inferred← citeshttps://doi.org/10.1109/micro.2005.38openalex-snapshot
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
inferred← citeshttps://doi.org/10.1109/micro.2006.20openalex-snapshot
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
inferred← citeshttps://doi.org/10.1109/pact.1998.727261openalex-snapshot
Dynamic hammock predication for non-predicated instruction set architectures
inferred← citeshttps://doi.org/10.1145/2677037openalex-snapshot
Efficient Out-of-Order Execution of Guarded ISAs
inferred← citeshttps://doi.org/10.1145/335231.335251openalex-snapshot
Using profiling to reduce branch misprediction costs on a dynamically scheduled processor
inferred← citeshttps://doi.org/10.1145/782814.782840openalex-snapshot
Predicate prediction for efficient out-of-order execution
inferred← citeshttps://doi.org/10.1145/782837.782840openalex-snapshot
Predicate prediction for efficient out-of-order execution
inferred← citeshttps://doi.org/10.1177/10943420251348799openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part I: General-purpose processors and hardware accelerators
inferred← citeshttps://doi.org/10.5296/jpag.v3i3.6222openalex-snapshot
Impact of Effective Training Program, Job Satisfaction and Reward Management System on the Employee Motivation with mediating role of Employee Commitment
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93337openalex-snapshot
Predicated execution and register windows for out-of-order processors
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.