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Compiler algorithms on if-conversion, speculative predicates assignment and predicated code optimizations

https://doi.org/10.1007/bfb0017250
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3200-2_4openalex-snapshot
The Multiflow Trace Scheduling Compiler
inferredcites →https://doi.org/10.1007/978-1-4615-3200-2_6openalex-snapshot
Compiling for the Cydra 5
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1007/bf01205184openalex-snapshot
Compiling for the Cydra
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/micro.1992.697013openalex-snapshot
Enhanced Modulo Scheduling For Loops With Conditional Branches
inferredcites →https://doi.org/10.1109/superc.1990.130021openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/106972.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/115952.115979openalex-snapshot
IMPACT
inferredcites →https://doi.org/10.1145/115952.115980openalex-snapshot
Single instruction stream parallelism is greater than two
inferredcites →https://doi.org/10.1145/144965.145796openalex-snapshot
Enhanced modulo scheduling for loops with conditional branches
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.5555/110382.110438openalex-snapshot
Parallelization of loops with exits on pipelined architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4419-6345-1_21openalex-snapshot
C Compilers and Code Optimization for DSPs
inferred← citeshttps://doi.org/10.1007/978-1-4614-6859-2_31openalex-snapshot
C Compilers and Code Optimization for DSPs
inferred← citeshttps://doi.org/10.1007/978-3-540-27866-5_43openalex-snapshot
If-Conversion in SSA Form
inferred← citeshttps://doi.org/10.1007/978-3-540-45099-3_14openalex-snapshot
Partial Redundancy Elimination on Predicated Code
inferred← citeshttps://doi.org/10.1007/978-3-642-54807-9_1openalex-snapshot
Using the SSA-Form in a Code Generator
inferred← citeshttps://doi.org/10.1109/estmed.2007.4375809openalex-snapshot
Leveraging Predicated Execution for Multimedia Processing
inferred← citeshttps://doi.org/10.1109/micro.2001.991116openalex-snapshot
Efficient static single assignment form for predication
inferred← citeshttps://doi.org/10.1109/pact.1997.644007openalex-snapshot
Path profile guided partial dead code elimination using predication
inferred← citeshttps://doi.org/10.1134/s199508022213042xopenalex-snapshot
Parallelism Detection Using Graph Labelling
inferred← citeshttps://doi.org/10.1145/1269843.1269859openalex-snapshot
Improvements to the Psi-SSA representation
inferred← citeshttps://doi.org/10.1145/1698759.1698762openalex-snapshot
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques
inferred← citeshttps://doi.org/10.1145/2443608.2443611openalex-snapshot
IR-level versus machine-level if-conversion for predicated architectures
inferred← citeshttps://doi.org/10.1145/2568326.2568327openalex-snapshot
Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture
inferred← citeshttps://doi.org/10.1145/3356842openalex-snapshot
Evaluating Auto-Vectorizing Compilers through Objective Withdrawal of Useful Information
inferred← citeshttps://doi.org/10.1145/354880.354894openalex-snapshot
Code generator optimizations for the ST120 DSP-MCU core
inferred← citeshttps://doi.org/10.1504/ijes.2009.027236openalex-snapshot
If-conversion for embedded VLIW architectures
inferred← citeshttps://doi.org/10.22360/springsim.2016.hpc.041openalex-snapshot
Optimality Analysis of If-Conversion Transformation
inferred← citeshttps://doi.org/10.48550/arxiv.0705.2126openalex-snapshot
Improvements to the Psi-SSA representation
inferred← citeshttps://doi.org/10.48550/arxiv.1603.01112openalex-snapshot
If-Conversion Optimization using Neuro Evolution of Augmenting Topologies
inferred← citeshttps://doi.org/10.5555/522659.825652openalex-snapshot
Path profile guided partial dead code elimination using predication
inferred← citeshttps://doi.org/10.5555/563998.564022openalex-snapshot
Efficient static single assignment form for predication
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