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Global register allocation based on graph fusion

https://doi.org/10.1007/bfb0017257
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4471-3501-2_9openalex-snapshot
Phase Ordering of Register Allocation and Instruction Scheduling
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1007/bf01205185openalex-snapshot
The superblock: An effective technique for VLIW and superscalar compilation
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1109/micro.1995.476823openalex-snapshot
Region-based compilation: an introduction and motivation
inferredcites →https://doi.org/10.1145/113445.113451openalex-snapshot
Predicting program behavior using real or estimated profiles
inferredcites →https://doi.org/10.1145/113445.113462openalex-snapshot
Register allocation via hierarchical graph coloring
inferredcites →https://doi.org/10.1145/115952.115979openalex-snapshot
IMPACT
inferredcites →https://doi.org/10.1145/12276.13321openalex-snapshot
Effectiveness of a machine-level, global optimizer
inferredcites →https://doi.org/10.1145/143365.143493openalex-snapshot
Predicting conditional branch directions from previous runs of a program
inferredcites →https://doi.org/10.1145/155090.155116openalex-snapshot
Load/store range analysis for global register allocation
inferredcites →https://doi.org/10.1145/173262.155116openalex-snapshot
Load/store range analysis for global register allocation
inferredcites →https://doi.org/10.1145/178243.178420openalex-snapshot
Zero-cost range splitting
inferredcites →https://doi.org/10.1145/178243.178427openalex-snapshot
Register allocation over the program dependence graph
inferredcites →https://doi.org/10.1145/73141.74841openalex-snapshot
Spill code minimization techniques for optimizing compliers
inferredcites →https://doi.org/10.1145/73141.74843openalex-snapshot
Coloring heuristics for register allocation
inferredcites →https://doi.org/10.1145/74818.74841openalex-snapshot
Spill code minimization techniques for optimizing compliers
inferredcites →https://doi.org/10.1145/88616.88621openalex-snapshot
The priority-based coloring approach to register allocation
inferredcites →https://doi.org/10.1145/989393.989424openalex-snapshot
Coloring heuristics for register allocation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-74061-2_10openalex-snapshot
A Framework for End-to-End Verification and Evaluation of Register Allocators
inferred← citeshttps://doi.org/10.1109/micro.2002.1176254openalex-snapshot
A faster optimal register allocator
inferred← citeshttps://doi.org/10.1109/pact.1998.727246openalex-snapshot
Optimistic register coalescing
inferred← citeshttps://doi.org/10.1109/qest.2004.11openalex-snapshot
Genetic Instruction Scheduling and Register Allocation
inferred← citeshttps://doi.org/10.1145/236337.236342openalex-snapshot
Code reuse in an optimizing compiler
inferred← citeshttps://doi.org/10.1145/258915.258926openalex-snapshot
tcc
inferred← citeshttps://doi.org/10.1145/258915.258942openalex-snapshot
Call-cost directed register allocation
inferred← citeshttps://doi.org/10.1145/277650.277740openalex-snapshot
Fast, effective code generation in a just-in-time Java compiler
inferred← citeshttps://doi.org/10.1145/2972206.2972211openalex-snapshot
Trace-based Register Allocation in a JIT Compiler
inferred← citeshttps://doi.org/10.1145/3237009.3237010openalex-snapshot
Parallel trace register allocation
inferred← citeshttps://doi.org/10.1145/353926.353929openalex-snapshot
Fusion-based register allocation
inferred← citeshttps://doi.org/10.1145/378795.378854openalex-snapshot
Optimal spilling for CISC machines with few registers
inferred← citeshttps://doi.org/10.1145/510857.510867openalex-snapshot
Efficient global register allocation for minimizing energy consumption
inferred← citeshttps://doi.org/10.1145/512529.512535openalex-snapshot
Preference-directed graph coloring
inferred← citeshttps://doi.org/10.5555/774861.774888openalex-snapshot
A faster optimal register allocator
inferred← citeshttps://doi.org/10.5555/942806.943850openalex-snapshot
Spill code minimization by spill code motion
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