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The superblock: An effective technique for VLIW and superscalar compilation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results
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Treegion scheduling for wide issue processors
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Trace cache redundancy: red and blue traces
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CARS: a new code generation framework for clustered ILP processors
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Inter-cluster communication models for clustered VLIW processors
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An Approach for Implementing Efficient Superscalar CISC Processors
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Software-Hardware Cooperative Memory Disambiguation
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Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs
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Exploring Potential Parallelism of Sequential Programs with Superblock Reordering
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A framework for energy estimation of VLIW architecture
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Speculative trace scheduling in VLIW processors
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Compiler-based frame formation for static optimization
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The heterogeneous block architecture
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Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency
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Architecture-dependent register allocation and instruction scheduling on VLIW
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Scheduling of conditional branches using SSA form for superscalar/VLIW processors
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A Novel Chaining Approach for Direct Control Transfer Instructions
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An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures
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High-level information-an approach for integrating front-end and back-end compilers
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Impact on performance of fused multiply-add units in aggressive VLIW architectures
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Optimization of instruction fetch for decision support workloads
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Aggressive compiler optimization and parallelization with thread-level speculation
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A Vector-µSIMD-VLIW Architecture for Multimedia Applications
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Instruction scheduling for VLIW processors under variation scenario
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Using compressed bytecode traces for slicing Java programs
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A Formalization of an Emulation Based Co-designed Virtual Machine
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Investigating a four-issue deterministic VLIW architecture for real-time systems
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Accuracy of profile maintenance in optimizing compilers
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Code size efficiency in global scheduling for ILP processors
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Code cache management schemes for dynamic optimizers
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A region-based compilation infrastructure
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Compiler-directed resource management for active code regions
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Analyis of Path Profiling Information Generated with Performance Monitoring Hardware
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A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit
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The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors
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A Constraint Programming Approach for Instruction Assignment
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