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Fine-grain scheduling under resource constraints
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-55895-0_462openalex-snapshot
A polynomial time method for optimal software pipelining
inferredcites →https://doi.org/10.1007/3-540-55895-0_463openalex-snapshot
Scheduling loops on parallel processors: A simple algorithm with close to optimum performance
inferredcites →https://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferredcites →https://doi.org/10.1007/bf01379404openalex-snapshot
Some efficient solutions to the affine scheduling problem. Part II. Multidimensional time
inferredcites →https://doi.org/10.1007/bf01407835openalex-snapshot
Some efficient solutions to the affine scheduling problem. I. One-dimensional time
inferredcites →https://doi.org/10.1007/bf01407931openalex-snapshot
Dataflow analysis of array and scalar references
inferredcites →https://doi.org/10.1109/mc.1984.1659185openalex-snapshot
The VLIW Machine: A Multiprocessor for Compiling Scientific Code
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards
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Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints
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Modulo Scheduling and Loop Pipelining
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Equimax: A New Formulation of Optimal Register-Sensitive Scheduling for ILP Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-71229-9_9openalex-snapshot
Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation
inferred← citeshttps://doi.org/10.1007/bfb0014189openalex-snapshot
An experimental study of an ILP-based exact solution method for software pipelining
inferred← citeshttps://doi.org/10.1007/bfb0014190openalex-snapshot
Insertion scheduling: An alternative to list scheduling for modulo schedulers
inferred← citeshttps://doi.org/10.1007/bfb0024784openalex-snapshot
Optimal software pipelining through enumeration of schedules
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2014.05.002openalex-snapshot
Communication storage optimization for static dataflow with access patterns under periodic scheduling and throughput constraint
inferred← citeshttps://doi.org/10.1023/a:1011136427062openalex-snapshot
Design of Processor Arrays for Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1023/a:1018742213548openalex-snapshot
Optimal Modulo Scheduling Through Enumeration
inferred← citeshttps://doi.org/10.1109/71.544355openalex-snapshot
A framework for resource-constrained rate-optimal software pipelining
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Circuit retiming applied to decomposed software pipelining
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Automatic data mapping of signal processing applications
inferred← citeshttps://doi.org/10.1109/asap.2000.862405openalex-snapshot
Generation of scheduling functions supporting LSGP-partitioning
inferred← citeshttps://doi.org/10.1109/fpga.2002.1106692openalex-snapshot
Automatic latency-optimal design of FPGA-based systolic arrays
inferred← citeshttps://doi.org/10.1109/intera.2004.1299506openalex-snapshot
Exploitation of instruction-level parallelism for optimal loop scheduling
inferred← citeshttps://doi.org/10.1109/ispan.2004.1300478openalex-snapshot
Optimal loop scheduling with register constraints using flow graphs
inferred← citeshttps://doi.org/10.1109/isss.1999.814263openalex-snapshot
Loop alignment for memory accesses optimization
inferred← citeshttps://doi.org/10.1109/rtcsa50079.2020.9203667openalex-snapshot
Cyclic Scheduling of Loop-Intensive Applications on Heterogeneous Multiprocessor Architectures
inferred← citeshttps://doi.org/10.1145/237578.237613openalex-snapshot
A new guaranteed heuristic for the software pipelining problem
inferred← citeshttps://doi.org/10.1145/2597809.2597825openalex-snapshot
Improving performance of loops on DIAM-based VLIW architectures
inferred← citeshttps://doi.org/10.1145/2658993openalex-snapshot
A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving Theories
inferred← citeshttps://doi.org/10.1145/291891.291901openalex-snapshot
Automatic data layout for distributed-memory machines
inferred← citeshttps://doi.org/10.1201/9781420043839.ch20openalex-snapshot
Advances in Software Pipelining
inferred← citeshttps://doi.org/10.70675/a54daae5z5f73z4642zb7b6z977855f1da8dopenalex-snapshot
Deployment of loop-intensive applications on heterogeneous multiprocessor architectures
inferred← citeshttps://doi.org/10.70675/ceece872z48a1z47e3zba4ez2753b8df5fe5openalex-snapshot
Génération de code polyédrique efficace : vers plus de parallélisme et moins de contrôle
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