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Iterative Modulo Scheduling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Scheduling loops on parallel processors: A simple algorithm with close to optimum performance
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Languages and Compilers for Parallel Computing
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The multiflow trace scheduling compiler
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The cydra 5 minisupercomputer: Architecture and implementation
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The superblock: An effective technique for VLIW and superscalar compilation
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Efficient instruction scheduling using finite state automata
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Fine-grain scheduling under resource constraints
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Data flow and dependence analysis for instruction level parallelism
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University of Illinois at Urbana-Champaign
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The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
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An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
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The benefit of predicated execution for software pipelining
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Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1993.282761openalex-snapshot
Instruction scheduling for the Motorola 88110
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A VLIW architecture based on shifting register files
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Parallelization of loops with exits on pipelined architectures
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A Preliminary Evaluation of the Critical Path Method for Scheduling Tasks on Multiprocessor Systems
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Optimal Scheduling Strategies in a Multiprocessor System
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Trace Scheduling: A Technique for Global Microcode Compaction
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On Algorithms for Enumerating All Circuits of a Graph
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Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
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Monte Carlo techniques in code optimization
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Genetic algorithms and instruction scheduling
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Register allocation for software pipelined loops
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A non-deterministic scheduler for a software pipelining compiler
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An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
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Code generation schema for modulo scheduled loops
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Lifetime-sensitive modulo scheduling
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Highly concurrent scalar processing
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Height reduction of control recurrences for ILP processors
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Minimum register requirements for a modulo schedule
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Minimizing register requirements under resource-constrained rate-optimal software pipelining
inferredcites →https://doi.org/10.1145/192724.192734openalex-snapshot
Software pipelining with register allocation and spilling
inferredcites →https://doi.org/10.1145/192724.192755openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
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The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/255129.255153openalex-snapshot
Loop optimization for horizontal microcoded machines
inferredcites →https://doi.org/10.1145/255305.255317openalex-snapshot
A compilation technique for software pipelining of loops with conditional jumps
inferredcites →https://doi.org/10.1145/2591635.2667171openalex-snapshot
Optimum modulo schedules for minimum register requirements
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Software pipelining: an effective scheduling technique for VLIW machines
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Conversion of control dependence to data dependence
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Improving register allocation for subscripted variables
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Unrolling-based optimizations for modulo scheduling
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Stage scheduling: a technique to reduce the register requirements of a module schedule
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique
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Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
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Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs
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Loop Shifting for Loop Compaction
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FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors
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Modulo Scheduling and Loop Pipelining
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Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs
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Mapping streaming architectures on reconfigurable platforms
inferred← citeshttps://doi.org/10.1145/1375657.1375678openalex-snapshot
Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays
inferred← citeshttps://doi.org/10.1145/1706299.1706311openalex-snapshot
A simple, verified validator for software pipelining
inferred← citeshttps://doi.org/10.1145/1707801.1706311openalex-snapshot
A simple, verified validator for software pipelining
inferred← citeshttps://doi.org/10.1145/2579676openalex-snapshot
Predicate-aware, makespan-preserving software pipelining of scheduling tables
inferred← citeshttps://doi.org/10.1145/258915.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/258916.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/2629547openalex-snapshot
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
inferred← citeshttps://doi.org/10.1145/2764967.2764968openalex-snapshot
Efficient Compilation of Stream Programs for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1145/3174243.3174264openalex-snapshot
Dynamically Scheduled High-level Synthesis
inferred← citeshttps://doi.org/10.1145/3316781.3317842openalex-snapshot
Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning
inferred← citeshttps://doi.org/10.1145/3317670openalex-snapshot
Exact and Practical Modulo Scheduling for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/337292.337431openalex-snapshot
Predicting performance potential of modern DSPs
inferred← citeshttps://doi.org/10.1145/3373087.3375314openalex-snapshot
Buffer Placement and Sizing for High-Performance Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3477053openalex-snapshot
Buffer Placement and Sizing for High-Performance Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3597614openalex-snapshot
Resource Sharing in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/360276.360322openalex-snapshot
Attacking the semantic gap between application programming languages and configurable hardware
inferred← citeshttps://doi.org/10.1145/3663675openalex-snapshot
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
inferred← citeshttps://doi.org/10.1145/368434.368588openalex-snapshot
Offline program re-mapping to improve branch prediction efficiency in embedded systems
inferred← citeshttps://doi.org/10.1145/368434.368766openalex-snapshot
Retargetable estimation scheme for DSP architecture selection
inferred← citeshttps://doi.org/10.1145/3705732openalex-snapshot
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3766063openalex-snapshot
MoDAF: A Multi-objective Divide-and-Conquer Parameter Tuning Framework for CGRAs
inferred← citeshttps://doi.org/10.1145/503048.503075openalex-snapshot
Performance-constrained pipelining of software loops onto reconfigurable hardware
inferred← citeshttps://doi.org/10.1145/504914.504921openalex-snapshot
Constructing and exploiting linear schedules with prescribed parallelism
inferred← citeshttps://doi.org/10.1145/581630.581649openalex-snapshot
Cost effective memory disambiguation for multimedia codes
inferred← citeshttps://doi.org/10.1145/643470.643475openalex-snapshot
Static resource models for code-size efficient embedded processors
inferred← citeshttps://doi.org/10.1145/993396.993403openalex-snapshot
The design of dynamically reconfigurable datapath coprocessors
inferred← citeshttps://doi.org/10.1155/2008/516240openalex-snapshot
Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774520openalex-snapshot
PathSeeker: A Fast Mapping Algorithm for CGRAs
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992940openalex-snapshot
Monomorphism-Based CGRA Mapping Via Space and Time Decoupling
inferred← citeshttps://doi.org/10.23919/date64628.2025.10993073openalex-snapshot
PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA
inferred← citeshttps://doi.org/10.3390/electronics10050532openalex-snapshot
A Highly Configurable High-Level Synthesis Functional Pattern Library
inferred← citeshttps://doi.org/10.3390/electronics10212590openalex-snapshot
CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor
inferred← citeshttps://doi.org/10.3390/electronics14234578openalex-snapshot
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis
inferred← citeshttps://doi.org/10.48456/tr-660openalex-snapshot
Static program analysis based on virtual register renaming
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A Comparative Study of Scheduling Techniques for Multimedia Applications on SIMD Pipelines
inferred← citeshttps://doi.org/10.5555/1874620.1874752openalex-snapshot
Heterogeneous coarse-grained processing elements: a template architecture for embedded processing acceleration
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Multi-pumping for resource reduction in FPGA high-level synthesis
inferred← citeshttps://doi.org/10.5555/2555729.2555747openalex-snapshot
From software to accelerators with LegUp high-level synthesis
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GeMS: a generator for modulo scheduling problems: work in progress
inferred← citeshttps://doi.org/10.5555/339492.340023openalex-snapshot
Function unit specialization through code analysis
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Efficient Backtracking Instruction Schedulers
inferred← citeshttps://doi.org/10.5555/522344.825697openalex-snapshot
Efficient edge profiling for ILP-processors
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Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93321openalex-snapshot
Multilevel tiling for non-rectangular interation spaces
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Compiler Strategies for Transport Triggered Architectures.
inferred← citeshttps://doi.org/10.70675/ceece872z48a1z47e3zba4ez2753b8df5fe5openalex-snapshot
Génération de code polyédrique efficace : vers plus de parallélisme et moins de contrôle
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Using HLS to raise the design abstraction level for faster exploration of different CPU Micro-architectures
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