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BDD based procedures for a theory of equality with uninterpreted functions

https://doi.org/10.1007/bfb0028749
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-48683-6_39openalex-snapshot
Deciding Equality Formulas by Small Domains Instantiations
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-61474-5_95openalex-snapshot
VIS: A system for verification and synthesis
inferredcites →https://doi.org/10.1007/3-540-63166-6_32openalex-snapshot
Combining constraint solving and symbolic model checking for a class of systems with non-linear constraints
inferredcites →https://doi.org/10.1007/bfb0031808openalex-snapshot
Validity checking for combinations of theories with equality
inferredcites →https://doi.org/10.1007/bfb0031810openalex-snapshot
Verification using uninterpreted functions and finite instantiations
inferredcites →https://doi.org/10.1016/c2009-0-22107-6openalex-snapshot
A Mathematical Introduction to Logic
inferredcites →https://doi.org/10.1016/s0049-237x(13)72072-xopenalex-snapshot
Studies in Logic and The Foundations of Mathematics
inferredcites →https://doi.org/10.1057/jors.1991.155openalex-snapshot
Introduction to Algorithms
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/dac.1997.597155openalex-snapshot
Equivalence Checking Using Cuts And Heaps
inferredcites →https://doi.org/10.1109/iccad.1993.580029openalex-snapshot
Dynamic variable ordering for ordered binary decision diagrams
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1109/test.1989.82368openalex-snapshot
Efficient generation of test patterns using Boolean difference
inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot
Verification of arithmetic circuits with binary moment diagrams
inferredcites →https://doi.org/10.1145/266021.266090openalex-snapshot
Equivalence checking using cuts and heaps
inferredcites →https://doi.org/10.1145/309847.309967openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferredcites →https://doi.org/10.1145/322123.322137openalex-snapshot
A Practical Decision Procedure for Arithmetic with Function Symbols
inferredcites →https://doi.org/10.2307/2964059openalex-snapshot
W. Ackermann. Solvable cases of the decision problem. Studies in logic and the foundations of mathematics. North-Holland Publishing Company, Amsterdam1954, VIII + 114 pp.

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1006/inco.2002.3175openalex-snapshot
The Small Model Property: How Small Can It Be?
inferred← citeshttps://doi.org/10.1007/10722167_10openalex-snapshot
Boolean Satisfiability with Transitivity Constraints
inferred← citeshttps://doi.org/10.1007/10722167_24openalex-snapshot
Formal Verification of VLIW Microprocessors with Speculative Execution
inferred← citeshttps://doi.org/10.1007/11513988_32openalex-snapshot
Yet Another Decision Procedure for Equality Logic
inferred← citeshttps://doi.org/10.1007/11549345_66openalex-snapshot
A BDD-Representation for the Logic of Equality and Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/11560548_10openalex-snapshot
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units
inferred← citeshttps://doi.org/10.1007/3-540-36078-6_13openalex-snapshot
Using BDDs with Combinations of Theories
inferred← citeshttps://doi.org/10.1007/3-540-36126-x_10openalex-snapshot
On Solving Presburger and Linear Arithmetic with SAT
inferred← citeshttps://doi.org/10.1007/3-540-44404-1_11openalex-snapshot
Equational Binary Decision Diagrams
inferred← citeshttps://doi.org/10.1007/3-540-44585-4_13openalex-snapshot
Finite Instantiations in Equivalence Logic with Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/3-540-44585-4_20openalex-snapshot
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations
inferred← citeshttps://doi.org/10.1007/3-540-45294-x_27openalex-snapshot
Range Allocation for Equivalence Logic
inferred← citeshttps://doi.org/10.1007/3-540-45319-9_18openalex-snapshot
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
inferred← citeshttps://doi.org/10.1007/3-540-45620-1_35openalex-snapshot
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_5openalex-snapshot
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
inferred← citeshttps://doi.org/10.1007/3-540-48683-6_39openalex-snapshot
Deciding Equality Formulas by Small Domains Instantiations
inferred← citeshttps://doi.org/10.1007/3-540-48683-6_40openalex-snapshot
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/3-540-48754-9_1openalex-snapshot
Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_24openalex-snapshot
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_3openalex-snapshot
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
inferred← citeshttps://doi.org/10.1007/978-3-540-24698-5_56openalex-snapshot
A Proof System and a Decision Procedure for Equality Logic
inferred← citeshttps://doi.org/10.1007/978-3-540-24730-2_1openalex-snapshot
Revisiting Positive Equality
inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_13openalex-snapshot
An Experimental Evaluation of Ground Decision Procedures
inferred← citeshttps://doi.org/10.1007/978-3-540-30210-0_7openalex-snapshot
A Decision Procedure for Equality Logic with Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/978-3-540-45206-5_16openalex-snapshot
Automatic Abstraction of Equations in a Logic of Equality
inferred← citeshttps://doi.org/10.1007/978-3-540-74105-3openalex-snapshot
Decision Procedures: An Algorithmic Point of View
inferred← citeshttps://doi.org/10.1007/978-3-540-85762-4_16openalex-snapshot
A New Approach for the Construction of Multiway Decision Graphs
inferred← citeshttps://doi.org/10.1007/978-3-642-16901-4_24openalex-snapshot
Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
Machine Assisted Verification
inferred← citeshttps://doi.org/10.1016/j.entcs.2009.10.016openalex-snapshot
A Term Rewriting Technique for Decision Graphs
inferred← citeshttps://doi.org/10.1016/j.ic.2007.03.003openalex-snapshot
Generalizing DPLL and satisfiability for equalities
inferred← citeshttps://doi.org/10.1016/s0747-7171(02)00091-3openalex-snapshot
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors
inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80661-3openalex-snapshot
Transforming equality logic to propositional logic
inferred← citeshttps://doi.org/10.1023/a:1014170513439openalex-snapshot
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
inferred← citeshttps://doi.org/10.1109/aspdac.2004.1337587openalex-snapshot
Efficient translation of Boolean formulas to CNF in formal verification of microprocessors
inferred← citeshttps://doi.org/10.1109/aspdac.2004.1337588openalex-snapshot
Using positive equality to prove liveness for pipelined microprocessors
inferred← citeshttps://doi.org/10.1109/aspdac.2010.5419811openalex-snapshot
A method for debugging of pipelined processors in formal verification by Correspondence Checking
inferred← citeshttps://doi.org/10.1109/aspdac.2011.5722201openalex-snapshot
Automatic formal verification of reconfigurable DSPs
inferred← citeshttps://doi.org/10.1109/dac.1999.781348openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1109/date.2002.998246openalex-snapshot
Using rewriting rules and positive equality to formally verify wide-issue out-of-order microprocessors with a reorder buffer
inferred← citeshttps://doi.org/10.1109/date.2004.1268859openalex-snapshot
Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors
inferred← citeshttps://doi.org/10.1109/hldvt.2001.972816openalex-snapshot
Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core
inferred← citeshttps://doi.org/10.1109/hldvt.2004.1431231openalex-snapshot
Formal verification of pipelined processors with load-value prediction
inferred← citeshttps://doi.org/10.1109/iccd.2004.1347910openalex-snapshot
Comparative study of strategies for formal verification of high-level processors
inferred← citeshttps://doi.org/10.1109/isqed.2006.142openalex-snapshot
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
inferred← citeshttps://doi.org/10.1109/isqed.2014.6783383openalex-snapshot
Formal verification of safety of polymorphic heterogeneous multi-core architectures
inferred← citeshttps://doi.org/10.1109/test.2003.1270834openalex-snapshot
Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
inferred← citeshttps://doi.org/10.1145/309847.309967openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1145/337292.337331openalex-snapshot
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
inferred← citeshttps://doi.org/10.1145/371282.371364openalex-snapshot
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
inferred← citeshttps://doi.org/10.1145/988952.988975openalex-snapshot
Efficient formal verification of pipelined processors with instruction queues
inferred← citeshttps://doi.org/10.1613/jair.3196openalex-snapshot
Computing Small Unsatisfiable Cores in Satisfiability Modulo Theories
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.23919/date.2018.8341979openalex-snapshot
Symbolic quick error detection using symbolic initial state for pre-silicon verification
inferred← citeshttps://doi.org/10.3233/faia241007openalex-snapshot
Canonical Decision Diagrams Modulo Theories
inferred← citeshttps://doi.org/10.3233/sat190034openalex-snapshot
Lazy Satisfiability Modulo Theories
inferred← citeshttps://doi.org/10.3390/electronics8091057openalex-snapshot
Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification
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