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Validity checking for combinations of theories with equality
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Simple Word Problems in Universal Algebras
inferredcites →https://doi.org/10.1016/b978-0-08-012975-4.50028-xopenalex-snapshot
Simple Word Problems in Universal Algebras††The work reported in this paper was supported in part by the U.S. Office of Naval Research.
inferredcites →https://doi.org/10.1093/comjnl/34.1.2openalex-snapshot
An Introduction to Knuth-Bendix Completion
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Formal verification for fault-tolerant architectures: prolegomena to the design of PVS
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
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Computational Problems in Abstract Algebra
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Efficient validity checking for processor verification
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inferred← citeshttps://doi.org/10.1002/spe.556openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/1-4020-2530-0_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/11493853_24openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-63166-6_9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-24597-1_34openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-24698-5_56openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-24730-2_1openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_13openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_14openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_40openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_49openalex-snapshot
CVC Lite: A New Implementation of the Cooperating Validity Checker
inferred← citeshttps://doi.org/10.1007/978-3-540-30124-0_21openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-30210-0_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-30494-4_9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-31848-4_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-40007-3_24openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-45069-6_15openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-45069-6_33openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-45069-6_34openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-45085-6_16openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-73368-3_52openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-74105-3openalex-snapshot
Decision Procedures: An Algorithmic Point of View
inferred← citeshttps://doi.org/10.1007/978-3-642-04244-7_37openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-05089-3_6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0028737openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0028739openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0028749openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0031822openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0055343openalex-snapshot
Static analysis to identify invariants in RSML specifications
inferred← citeshttps://doi.org/10.1007/s10472-012-9322-xopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10766-005-0004-8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10817-006-9026-1openalex-snapshot
Design and Results of the First Satisfiability Modulo Theories Competition (SMT-COMP 2005)
inferred← citeshttps://doi.org/10.1016/j.apal.2004.10.005openalex-snapshot
Zero, successor and equality in BDDs
inferred← citeshttps://doi.org/10.1016/j.entcs.2004.09.042openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.entcs.2005.12.005openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.entcs.2008.12.089openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.ic.2004.10.006openalex-snapshot
A randomized satisfiability procedure for arithmetic and uninterpreted function symbols
inferred← citeshttps://doi.org/10.1016/j.ic.2004.11.001openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.jss.2004.03.034openalex-snapshot
ConSUS: a light-weight program conditioner
inferred← citeshttps://doi.org/10.1016/s0020-0255(97)10014-7openalex-snapshot
Addressing the shortcomings of traditional formal reasoning methods for concurrent programs: New tools and techniques for source code correctness
inferred← citeshttps://doi.org/10.1016/s0167-6423(99)00018-0openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80400-6openalex-snapshot
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inferred← citeshttps://doi.org/10.1023/a:1008700623084openalex-snapshot
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inferred← citeshttps://doi.org/10.1023/a:1014118529369openalex-snapshot
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inferred← citeshttps://doi.org/10.1023/a:1015707001763openalex-snapshot
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inferred← citeshttps://doi.org/10.1023/a:1022988809947openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/asap.2000.862377openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/aspdac.2006.1594639openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/dac.2003.1219039openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/dac.2006.229207openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/date.2000.840892openalex-snapshot
Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level
inferred← citeshttps://doi.org/10.1109/date.2005.127openalex-snapshot
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
inferred← citeshttps://doi.org/10.1109/hldvt.2001.972806openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hldvt.2001.972816openalex-snapshot
Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core
inferred← citeshttps://doi.org/10.1109/hldvt.2002.1224443openalex-snapshot
An equivalence checking methodology for hardware oriented C-based specifications
inferred← citeshttps://doi.org/10.1109/icasic.2003.1277479openalex-snapshot
System level design methodologies from the viewpoint of formal verification
inferred← citeshttps://doi.org/10.1109/iccad.1997.643402openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iccad.2005.1560082openalex-snapshot
RTL SAT simplification by boolean and interval arithmetic reasoning
inferred← citeshttps://doi.org/10.1109/icccas.2008.4657976openalex-snapshot
Constraints partitioning for RTL Satis ability solving by YICES
inferred← citeshttps://doi.org/10.1109/iccd.1999.808581openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iccms.2009.47openalex-snapshot
Formal Verification of Out-of-Order Processor
inferred← citeshttps://doi.org/10.1109/icfem.1997.630421openalex-snapshot
Systematic formal verification of interpreters
inferred← citeshttps://doi.org/10.1109/icsm.2000.883049openalex-snapshot
ConSIT: a conditioned program slicer
inferred← citeshttps://doi.org/10.1109/icsm.2001.972724openalex-snapshot
Pre/post conditioned slicing
inferred← citeshttps://doi.org/10.1109/icvd.2004.1260908openalex-snapshot
Formal verification of C language based VLSI designs
inferred← citeshttps://doi.org/10.1109/iscas.1999.777794openalex-snapshot
Synthesis of checker EFSMs from timing diagram specifications
inferred← citeshttps://doi.org/10.1109/isss.1998.730597openalex-snapshot
False path analysis based on a hierarchical control representation
inferred← citeshttps://doi.org/10.1109/lics.2001.932482openalex-snapshot
Successive approximation of abstract transition relations
inferred← citeshttps://doi.org/10.1109/wpc.2001.921717openalex-snapshot
Backward conditioning: a new program specialisation technique and its application to program comprehension
inferred← citeshttps://doi.org/10.1109/wpc.2004.1311051openalex-snapshot
Building executable union slices using conditioned slicing
inferred← citeshttps://doi.org/10.1145/1066100.1066102openalex-snapshot
Simplify: a theorem prover for program checking
inferred← citeshttps://doi.org/10.1145/1086228.1086284openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1118299.1118306openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1146909.1146971openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1217856.1217859openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1233501.1233664openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1292597.1292602openalex-snapshot
Refined typechecking with Stardust
inferred← citeshttps://doi.org/10.1145/277044.277186openalex-snapshot
A decision procedure for bit-vector arithmetic
inferred← citeshttps://doi.org/10.1145/298595.298603openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/343647.344347openalex-snapshot
Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level (poster paper)
inferred← citeshttps://doi.org/10.1145/349360.351125openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/371282.371364openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/378239.378265openalex-snapshot
Scalable hybrid verification of complex microprocessors
inferred← citeshttps://doi.org/10.1145/513829.513844openalex-snapshot
Automatic formal verification for scheduled VLIW code
inferred← citeshttps://doi.org/10.1145/775832.775945openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/996566.996628openalex-snapshot
An efficient finite-domain constraint solver for circuits
inferred← citeshttps://doi.org/10.1145/996566.996629openalex-snapshot
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inferred← citeshttps://doi.org/10.14288/1.0051649openalex-snapshot
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inferred← citeshttps://doi.org/10.14569/ijacsa.2016.070179openalex-snapshot
Verification of Statecharts Using Data Abstraction
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.1631/jzus.a0820812openalex-snapshot
Equality detection for linear arithmetic constraints
inferred← citeshttps://doi.org/10.21236/ada461197openalex-snapshot
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inferred← citeshttps://doi.org/10.26083/tuprints-00000113openalex-snapshot
Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
inferred← citeshttps://doi.org/10.48550/arxiv.cs/0402002openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.cs/9910014openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/266388.266456openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/380921.380927openalex-snapshot
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inferred← citeshttps://doi.org/10.5821/dissertation-2117-95294openalex-snapshot
Bounded model checking for asynchronous concurrent systems
inferred← citeshttps://doi.org/10.6083/m4kh0kkxopenalex-snapshot
Structuring instruction-sets with higher-order functions
inferred← citeshttps://doi.org/10.70675/6a3585eez5df3z474dzb64ez12a39e82b99dopenalex-snapshot
Formal Guaranties for Safety Critical Code Generation : the Case of Highly Variable Languages
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