On the public citation graph
*BMDs can delay the use of theorem proving for verifying arithmetic assembly instructions
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-49538-x_11openalex-snapshot
An Object-Oriented Framework for the Formal Verification of Processors
inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/3-540-56496-9_8openalex-snapshot
Higher-level specification and verification with BDDs
inferredcites →https://doi.org/10.1007/3-540-57826-9_140openalex-snapshot
Verification of the Tamarack-3 microprocessor in a hybrid verification environment
inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-60045-0_42openalex-snapshot
An integration of model checking with automated proof checking
inferredcites →https://doi.org/10.1007/3-540-60045-0_43openalex-snapshot
Automatic datapath abstraction in hardware systems
inferredcites →https://doi.org/10.1007/3-540-60275-5openalex-snapshot
Higher Order Logic Theorem Proving and Its Applications
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferredcites →https://doi.org/10.1016/0167-9260(89)90004-7openalex-snapshot
Formal specification and verification of microprocessor systems
inferredcites →https://doi.org/10.1016/b978-0-444-81641-2.50017-4openalex-snapshot
Automated high-level verification against clocked algorithmic specifications
inferredcites →https://doi.org/10.1109/12.368009openalex-snapshot
Formal modeling and verification of microprocessors
inferredcites →https://doi.org/10.1109/aspdac.1995.486361openalex-snapshot
Applying formal verification to a commercial microprocessor
inferredcites →https://doi.org/10.1109/dac.1995.249982openalex-snapshot
Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits
inferredcites →https://doi.org/10.1109/edtc.1996.494118openalex-snapshot
K*BMDs: a new data structure for verification
inferredcites →https://doi.org/10.1109/eurdac.1995.527438openalex-snapshot
Towards verifying VHDL descriptions of processors
inferredcites →https://doi.org/10.1109/iccad.1995.479995openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.1109/iccad.1995.480007openalex-snapshot
Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs
inferredcites →https://doi.org/10.1109/iccad.1995.480018openalex-snapshot
Binary decision diagrams and beyond: enabling technologies for formal verification
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1145/127601.127703openalex-snapshot
Using BDDs to verify multipliers
inferredcites →https://doi.org/10.1145/157485.164569openalex-snapshot
Spectral transforms for large boolean functions with applications to technology mapping
inferredcites →https://doi.org/10.1145/196244.196575openalex-snapshot
Formally verifying a microprocessor using a simulation methodology
inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot
Verification of arithmetic circuits with binary moment diagrams
inferredcites →https://doi.org/10.21236/ada281028openalex-snapshot
Verification of Arithmetic Functions with Binary Moment Diagrams
inferredcites →https://doi.org/10.21236/ada296684openalex-snapshot
Hybrid Decision Diagrams. Overcoming the Limitations of MTBDDs and BMDs,
inferredcites →https://doi.org/10.5555/113938.149642openalex-snapshot
Edge-valued binary decision diagrams for multi-level hierarchical verification
inferredcites →https://doi.org/10.5555/224270.224359openalex-snapshot
Towards verifying VHDL descriptions of processors
inferredcites →https://doi.org/10.5555/224841.224863openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.5555/224841.225047openalex-snapshot
Binary decision diagrams and beyond: enabling technologies for formal verification
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-63166-6_12openalex-snapshot
Automatic datapath extraction for efficient usage of HDD
inferred← citeshttps://doi.org/10.1007/978-0-387-35190-2_12openalex-snapshot
Implementation of a Multiple-Domain Decision Diagram Package
inferred← citeshttps://doi.org/10.1007/bfb0035377openalex-snapshot
Manipulation algorithms for K*BMDs
inferred← citeshttps://doi.org/10.1007/s100090100051openalex-snapshot
A word-level graph manipulation package
inferred← citeshttps://doi.org/10.1016/s0167-9260(02)00047-0openalex-snapshot
Minimization of Word-Level Decision Diagrams
inferred← citeshttps://doi.org/10.1109/date.1998.655921openalex-snapshot
Dynamic minimization of word-level decision diagrams
inferred← citeshttps://doi.org/10.1109/date.1999.761096openalex-snapshot
Formal verification of word-level specifications
inferred← citeshttps://doi.org/10.1109/iccd.2000.878312openalex-snapshot
Efficient dynamic minimization of word-level DDs based on lower bound computation
inferred← citeshttps://doi.org/10.1109/iccd.2005.52openalex-snapshot
Exploiting vanishing polynomials for equivalence verification of fixed-size arithmetic datapaths
inferred← citeshttps://doi.org/10.1109/icmss.2011.5999175openalex-snapshot
Equivalence Checking in Information System Hardware Design
inferred← citeshttps://doi.org/10.1109/iita.workshops.2008.188openalex-snapshot
Equivalence Checking for Intelligent Circuits
inferred← citeshttps://doi.org/10.1109/iscas.1999.777893openalex-snapshot
Grouping heuristics for word-level decision diagrams
inferred← citeshttps://doi.org/10.1109/tcad.2006.888277openalex-snapshot
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing
inferred← citeshttps://doi.org/10.1145/277044.277186openalex-snapshot
A decision procedure for bit-vector arithmetic
inferred← citeshttps://doi.org/10.1145/307418.307447openalex-snapshot
Formal verification of word-level specifications
inferred← citeshttps://doi.org/10.26053/0h-8eyy-yag0openalex-snapshot
Word-level abstractions for sequential design verification using algebraic geometry
inferred← citeshttps://doi.org/10.26053/0h-pxpd-6fg0openalex-snapshot
Word-level abstraction from combinational circuits using algebraic geometry
inferred← citeshttps://doi.org/10.5555/368058.368313openalex-snapshot
Dynamic minimization of word-level decision diagrams
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