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Verification of Arithmetic Functions with Binary Moment Diagrams

https://doi.org/10.21236/ada281028
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Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
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Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams
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Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams
inferred← citeshttps://doi.org/10.4018/jnmc.2009120903openalex-snapshot
The Synthesis of Stochastic Circuits for Nanoscale Computation
inferred← citeshttps://doi.org/10.4204/eptcs.359.11openalex-snapshot
Verified Implementation of an Efficient Term-Rewriting Algorithm for Multiplier Verification on ACL2
inferred← citeshttps://doi.org/10.4236/iim.2010.22012openalex-snapshot
Probabilistic Verification over GF(2m) Using Mod2-OBDDs
inferred← citeshttps://doi.org/10.48550/arxiv.1612.04588openalex-snapshot
Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic
inferred← citeshttps://doi.org/10.48550/arxiv.2010.03032openalex-snapshot
Symbolic Verification of Quantum Circuits
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Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
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The formal verification of a pipelined double-precision IEEE floating-point multiplier
inferred← citeshttps://doi.org/10.5555/224841.224862openalex-snapshot
Who are the variables in your neighbourhood
inferred← citeshttps://doi.org/10.5555/224841.224863openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
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Hybrid decision diagrams
inferred← citeshttps://doi.org/10.5555/2492708.2492935openalex-snapshot
Efficient Gröbner basis reductions for formal verification of galois field multipliers
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PHDD: an efficient graph representation for floating point circuit verification
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Dynamic minimization of word-level decision diagrams
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Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification
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