On the public citation graph
Quantifying the multi-level nature of tiling interactions
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-57659-2_18openalex-snapshot
Maximizing loop parallelism and improving data locality via loop fusion and distribution
inferredcites →https://doi.org/10.1007/bf01407835openalex-snapshot
Some efficient solutions to the affine scheduling problem. I. One-dimensional time
inferredcites →https://doi.org/10.1007/bfb0017243openalex-snapshot
Locality analysis for distributed shared-memory multiprocessors
inferredcites →https://doi.org/10.1007/bfb0038674openalex-snapshot
On estimating and enhancing cache effectiveness
inferredcites →https://doi.org/10.1016/0743-7315(88)90014-7openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1109/71.466632openalex-snapshot
Automatic partitioning of parallel loops and data arrays for distributed shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/71.97902openalex-snapshot
A loop transformation theory and an algorithm to maximize parallelism
inferredcites →https://doi.org/10.1109/icapp.1995.472180openalex-snapshot
A unifying framework for iteration reordering transformations
inferredcites →https://doi.org/10.1109/ipps.1995.395939openalex-snapshot
Hierarchical tiling for improved superscalar performance
inferredcites →https://doi.org/10.1109/micro.1995.476842openalex-snapshot
Unrolling-based optimizations for modulo scheduling
inferredcites →https://doi.org/10.1109/micro.1996.566468openalex-snapshot
Combining loop transformations considering caches and scheduling
inferredcites →https://doi.org/10.1109/pact.1996.552672openalex-snapshot
Combining optimization for cache and instruction-level parallelism
inferredcites →https://doi.org/10.1109/superc.1992.236704openalex-snapshot
Compiler blockability of numerical algorithms
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/109625.109631openalex-snapshot
Scanning polyhedra with DO loops
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/125826.125893openalex-snapshot
Tiling multidimensional iteration spaces for nonshared memory machines
inferredcites →https://doi.org/10.1145/143095.143132openalex-snapshot
A general framework for iteration-reordering loop transformations
inferredcites →https://doi.org/10.1145/143369.143427openalex-snapshot
Optimizing for parallelism and data locality
inferredcites →https://doi.org/10.1145/195473.195557openalex-snapshot
Compiler optimizations for improving data locality
inferredcites →https://doi.org/10.1145/197320.197366openalex-snapshot
Improving the ratio of memory operations to floating-point operations in loops
inferredcites →https://doi.org/10.1145/197405.197406openalex-snapshot
Compiler transformations for high-performance computing
inferredcites →https://doi.org/10.1145/207110.207162openalex-snapshot
Tile size selection using cache organization and data layout
inferredcites →https://doi.org/10.1145/2591635.2667164openalex-snapshot
Optimizing for parallelism and data locality
inferredcites →https://doi.org/10.1145/263699.263716openalex-snapshot
Determining the idle time of a tiling
inferredcites →https://doi.org/10.1145/7902.7904openalex-snapshot
Advanced compiler optimizations for supercomputers
inferredcites →https://doi.org/10.5555/225160.225209openalex-snapshot
Unrolling-based optimizations for modulo scheduling
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-49530-4_5openalex-snapshot
Loop Transformations for Hierarchical Parallelism and Locality
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_12openalex-snapshot
A Comparison of Compiler Tiling Algorithms
inferred← citeshttps://doi.org/10.1023/a:1008134522009openalex-snapshot
Improving Memory Traffic by Assembly-Level Exploitation of Reuses for Vector Registers
inferred← citeshttps://doi.org/10.1023/b:supe.0000011386.69245.f5openalex-snapshot
Transforming Complex Loop Nests for Locality
inferred← citeshttps://doi.org/10.1109/cgo.2005.10openalex-snapshot
Combining Models and Guided Empirical Search to Optimize for Multiple Levels of the Memory Hierarchy
inferred← citeshttps://doi.org/10.1109/cgo.2013.6495008openalex-snapshot
Defensive loop tiling for shared cache
inferred← citeshttps://doi.org/10.1109/dsd.2008.24openalex-snapshot
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
inferred← citeshttps://doi.org/10.1109/icpp.2002.1040857openalex-snapshot
Analysis of memory hierarchy performance of block data layout
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213377openalex-snapshot
ECO: an empirical-based compilation and optimization system
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370641openalex-snapshot
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
inferred← citeshttps://doi.org/10.1109/parelec.2006.33openalex-snapshot
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels
inferred← citeshttps://doi.org/10.1109/sc.2000.10015openalex-snapshot
Tiling Optimizations for 3D Scientific Computations
inferred← citeshttps://doi.org/10.1109/sc.2002.10054openalex-snapshot
On Increasing Architecture Awareness in Program Optimizations to Bridge the Gap between Peak and Sustained Processor Performance - Matrix-Multiply Revisited
inferred← citeshttps://doi.org/10.1109/tpds.2003.1189587openalex-snapshot
On the parallel execution time of tiled loops
inferred← citeshttps://doi.org/10.1145/1065895.1065898openalex-snapshot
Automatic blocking of QR and LU factorizations for locality
inferred← citeshttps://doi.org/10.1145/305619.305641openalex-snapshot
Selecting tile shape for minimal execution time
inferred← citeshttps://doi.org/10.1145/331532.331534openalex-snapshot
Locality optimizations for multi-level caches
inferred← citeshttps://doi.org/10.1145/378795.378859openalex-snapshot
Exact analysis of the cache behavior of nested loops
inferred← citeshttps://doi.org/10.1177/1094342004041295openalex-snapshot
Cache-Efficient Multigrid Algorithms
inferred← citeshttps://doi.org/10.25560/5589openalex-snapshot
Indexed dependence metadata and its applications in software performance optimisation
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.3717openalex-snapshot
Search-based Model-driven Loop Optimizations for Tensor Contractions
inferred← citeshttps://doi.org/10.5555/762761.762764openalex-snapshot
On Increasing Architecture Awareness in Program Optimizations to Bridge the Gap between Peak and Sustained Processor Performance — Matrix-Multiply Revisited
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93321openalex-snapshot
Multilevel tiling for non-rectangular interation spaces
inferred← citeshttps://doi.org/10.7282/t3cz3bqvopenalex-snapshot
A Framework for Qualitative Performance Prediction
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