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Detecting races in relay ladder logic programs

https://doi.org/10.1007/bfb0054172
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-69850-0_12openalex-snapshot
DESIGN AND SYNTHESIS OF SYNCHRONIZATION SKELETONS USING BRANCHING TIME TEMPORAL LOGIC
inferredcites →https://doi.org/10.1007/bf01383968openalex-snapshot
Verification of the Futurebus+ cache coherence protocol
inferredcites →https://doi.org/10.1016/b978-0-444-81641-2.50007-1openalex-snapshot
Verification of the Futurebus+ Cache Coherence Protocol**This research was sponsored in part by the Avionics Laboratory, Wright Research and Development Center, Aeronautical Systems Division (AFSC), U.S. Air Force, Wright-Patterson AFB, Ohio 45433-6543 under Contract F33615-90-C-1465, ARPA Order…
inferredcites →https://doi.org/10.1049/ip-e.1986.0034openalex-snapshot
Automatic verification of asynchronous circuits using temporal logic
inferredcites →https://doi.org/10.1049/ip-e:19860034openalex-snapshot
Automatic verification of asynchronous circuits using temporal logic
inferredcites →https://doi.org/10.1109/5.533956openalex-snapshot
Principles and methods of testing finite state machines-a survey
inferredcites →https://doi.org/10.1109/cmpass.1995.521884openalex-snapshot
Integrating formal methods and testing for concurrent programs
inferredcites →https://doi.org/10.1109/tc.1986.1676711openalex-snapshot
Automatic Verification of Sequential Circuits Using Temporal Logic
inferredcites →https://doi.org/10.1145/165180.165188openalex-snapshot
Type inclusion constraints and type inference
inferredcites →https://doi.org/10.1145/174675.177847openalex-snapshot
Soft typing with conditional types
inferredcites →https://doi.org/10.1145/356674.356676openalex-snapshot
Data Flow Analysis in Software Reliability
inferredcites →https://doi.org/10.1145/5397.5399openalex-snapshot
Automatic verification of finite-state concurrent systems using temporal logic specifications
inferredcites →https://doi.org/10.1184/r1/6604769openalex-snapshot
Design and Synthesis of Synchronization Skeletons Using Branching Time Temporal Logic
inferredcites →https://doi.org/10.7551/mitpress/2319.001.0001openalex-snapshot
The Definition of Standard ML

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Z-Ranking: Using Statistical Analysis to Counter the Impact of Static Analysis Approximations
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Memory-Model-Sensitive Data Race Analysis
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Ladder Metamodeling and PLC Program Validation through Time Petri Nets
inferred← citeshttps://doi.org/10.1007/978-3-642-34026-0_35openalex-snapshot
Model-Based Static Code Analysis for MATLAB Models
inferred← citeshttps://doi.org/10.1007/bfb0055513openalex-snapshot
A toolkit for constructing type- and constraint-based program analyses
inferred← citeshttps://doi.org/10.1016/j.cola.2021.101087openalex-snapshot
Language impact on productivity for industrial end users: A case study from Programmable Logic Controllers
inferred← citeshttps://doi.org/10.1016/s1383-7621(02)00061-9openalex-snapshot
Virtual prototyping of PLC-based embedded system using object model of target and behavior model by converting RLL-to-statechart directly
inferred← citeshttps://doi.org/10.1109/ccta41146.2020.9206344openalex-snapshot
Formal Verification of the Race Condition Vulnerability in Ladder Programs
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Functional safety certification: Practice and issues
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ICSTracker: Backtracking Intrusions in Modern Industrial Control Systems
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Model-based verification of PLC programs using Simulink design
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A model-driven engineering approach to formal verification of PLC programs
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Formal Verification of Safety and Liveness Properties for Logic Controllers. A Tool Comparison
inferred← citeshttps://doi.org/10.1109/secpri.2002.1004368openalex-snapshot
Using programmer-written compiler extensions to catch security holes
inferred← citeshttps://doi.org/10.1109/sp.2019.00034openalex-snapshot
Towards Automated Safety Vetting of PLC Code in Real-World Plants
inferred← citeshttps://doi.org/10.1109/tse.2003.1237172openalex-snapshot
Using redundancies to find errors
inferred← citeshttps://doi.org/10.1145/1029894.1029909openalex-snapshot
Correlation exploitation in error ranking
inferred← citeshttps://doi.org/10.1145/3106237.3106245openalex-snapshot
Symbolic execution of programmable logic controller code
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Bugs as deviant behavior
inferred← citeshttps://doi.org/10.1145/502034.502042openalex-snapshot
An empirical study of operating systems errors
inferred← citeshttps://doi.org/10.1145/587051.587060openalex-snapshot
Using redundancies to find errors
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.1525openalex-snapshot
Deductive formal verification of embedded systems
inferred← citeshttps://doi.org/10.48550/arxiv.2109.12774openalex-snapshot
Cyber-Physical Taint Analysis in Multi-stage Manufacturing Systems (MMS): A Case Study
inferred← citeshttps://doi.org/10.70675/dc3a6079z8ba1z4f9dz81a1zb7eb47e17f38openalex-snapshot
Methods and tools for the integration of formal verification in domain-specific languages
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