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Automatic verification of asynchronous circuits using temporal logic
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-10235-3openalex-snapshot
A Calculus of Communicating Systems
inferredcites →https://doi.org/10.1109/focs.1967.34openalex-snapshot
The general synthesis problem for asynchronous digital networks
inferredcites →https://doi.org/10.1109/sfcs.1981.44openalex-snapshot
Temporal logic can be more expressive
inferredcites →https://doi.org/10.1145/567067.567080openalex-snapshot
Automatic verification of finite state concurrent system using temporal logic specifications
inferredcites →https://doi.org/10.1184/r1/6603728openalex-snapshot
Automatic and hierarchical verification of asynchronous circuits using temporal logic
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A synthesis of two approaches for verifying finite state concurrent systems
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A Novel Strategy for Formal Verication of Asynchronous Circuit Design in PAiD tool
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