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Constructing hardware-software systems from a single description
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-18203-9_2openalex-snapshot
Communicating process architecture: Transputers and occam
inferredcites →https://doi.org/10.1007/3-540-57840-4_24openalex-snapshot
Hardware and software: The closing gap
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Using reconfigurable hardware to speed up product development and performance
inferredcites →https://doi.org/10.1007/978-3-642-77572-7_12openalex-snapshot
Refinement algebra proves correctness of compilation
inferredcites →https://doi.org/10.1007/bf01214557openalex-snapshot
Retargeting a hardware compiler using protocol converters
inferredcites →https://doi.org/10.1007/bf02811340openalex-snapshot
A hardware implementation of pure ESTEREL
inferredcites →https://doi.org/10.1007/bfb0021726openalex-snapshot
Towards a provably correct hardware implementation of occam
inferredcites →https://doi.org/10.1007/bfb0024175openalex-snapshot
An approach to verifiable compiling specification and prototyping
inferredcites →https://doi.org/10.1016/0141-9331(92)90034-qopenalex-snapshot
Design and verification of a highly concurrent machine
inferredcites →https://doi.org/10.1016/0304-3975(88)90049-7openalex-snapshot
The laws of OCCAM programming
inferredcites →https://doi.org/10.1016/b978-0-444-89901-9.50019-7openalex-snapshot
Hardware Compilation
inferredcites →https://doi.org/10.1017/cbo9780511811326openalex-snapshot
ML for the Working Programmer
inferredcites →https://doi.org/10.1109/async.1994.656286openalex-snapshot
Retargeting a hardware compiler proof using protocol converters
inferredcites →https://doi.org/10.1109/edac.1991.206431openalex-snapshot
The VLSI-programming language Tangram and its translation into handshake circuits
inferredcites →https://doi.org/10.1109/fpga.1993.279478openalex-snapshot
A field programmable accelerator for compiled-code applications
inferredcites →https://doi.org/10.1109/fpga.1994.315604openalex-snapshot
Hardware-software codesign of multidimensional programs
inferredcites →https://doi.org/10.1109/hsc.1994.336708openalex-snapshot
Towards a declarative framework for hardware-software codesign
inferredcites →https://doi.org/10.5555/947185.947214openalex-snapshot
Towards a declarative framework for hardware-software codesign
inferredcites →https://doi.org/10.5555/951513.951597openalex-snapshot
The VLSI-programming language Tangram and its translation into handshake circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Reconfigurable Computing
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Design of Highly Parallel Architectures with Alpha and Handel
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Hardware compilation, configurable platforms and ASICs for self-validating sensors
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Accelerating Simulation with FPGAs
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A Common Framework for Mixed Hardware/Software Systems
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A denotational semantics for Handel-C
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Verification of SpecC using predicate abstraction
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Reconfigurable processor architectures
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Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture
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Cluster of re-configurable nodes for scanning large genomic banks
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Reconfigurable Computing for Digital Signal Processing: A Survey
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Floating Point Verification in HOL Light: The Exponential Function
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An Approach to the Specification and Verification of a Hardware Compilation Scheme
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A Compositional Framework for Hardware/Software Co-Design
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Hardware/software co-design for virtual machines
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Hardware compilation for software engineers: An ATM example
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Design methodology for construction of asynchronous pipelines with Handel-C
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Hardware compilation: translating programs into circuits
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System specification experiments on a common benchmark
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Autonomous distributed self-organizing and self-healing hardware architecture - The eDNA concept
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eDNA: A Bio-Inspired Reconfigurable Hardware Cell Architecture Supporting Self-organisation and Self-healing
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Optimizing HW/SW codesign towards reliability for critical-application systems
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Development of a Bit-Level Compiler for Massively Parallel Vision Chips
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Hardware compilation for FPGA-based configurable computing machines
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Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
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Accurate area and delay estimators for FPGAs
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Design and Application of a Scalable Embedded Systems’ Architecture with an FPGA Based Operating Infrastucture
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Agile hardware development with rapid hardware definition language
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Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation
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Bandwidth Management with a Reconfigurable Data Cache
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Support of cross calls between a microprocessor and FPGA in CPU-FPGA coupling architecture
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Verification of specC using predicate abstraction
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Formal verification of SystemC by automatic hardware/software partitioning
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Hardware compilation for FPGA-based configurable computing machines
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Behavioral consistency of C and verilog programs using bounded model checking
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Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm
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Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
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Large-Scale, Parallel Embedded Applications: A Hardware Design Model for Software Engineers
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