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Herbrand automata for hardware verification

https://doi.org/10.1007/bfb0055616
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-59047-1_53openalex-snapshot
A tutorial on using PVS for hardware verification
inferredcites →https://doi.org/10.1007/3-540-61474-5_68openalex-snapshot
A platform for combining deductive with algorithmic verification
inferredcites →https://doi.org/10.1007/3-540-63166-6_22openalex-snapshot
Model checking in a microprocessor design project
inferredcites →https://doi.org/10.1007/bf00122419openalex-snapshot
Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods
inferredcites →https://doi.org/10.1007/bfb0031796openalex-snapshot
The need for formal methods for integrated circuit design
inferredcites →https://doi.org/10.1007/bfb0031797openalex-snapshot
Verification of all circuits in a floating-point unit using word-level model checking
inferredcites →https://doi.org/10.1007/bfb0031810openalex-snapshot
Verification using uninterpreted functions and finite instantiations
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/s0022-0000(70)80022-8openalex-snapshot
On formalised computer programs
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1109/tc.1986.1676711openalex-snapshot
Automatic Verification of Sequential Circuits Using Temporal Logic
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/567446.567453openalex-snapshot
Synchronous schemes and their decision problems
inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot
Efficient validity checking for processor verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11560548_10openalex-snapshot
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units
inferred← citeshttps://doi.org/10.1007/3-540-48683-6_40openalex-snapshot
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_23openalex-snapshot
Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study
inferred← citeshttps://doi.org/10.1007/978-3-540-68237-0_5openalex-snapshot
CoVaC: Compiler Validation by Program Analysis of the Cross-Product
inferred← citeshttps://doi.org/10.1007/978-3-540-85762-4_16openalex-snapshot
A New Approach for the Construction of Multiway Decision Graphs
inferred← citeshttps://doi.org/10.1007/978-3-642-35702-2_8openalex-snapshot
Hazard Analysis for Technical Systems
inferred← citeshttps://doi.org/10.1007/s11390-011-9421-xopenalex-snapshot
NuMDG: A New Tool for Multiway Decision Graphs Construction
inferred← citeshttps://doi.org/10.1016/s1571-0661(04)00186-0openalex-snapshot
Analyzing Automata with Presburger Arithmetic and Uninterpreted Function Symbols
inferred← citeshttps://doi.org/10.1145/3649329.3655958openalex-snapshot
SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution
inferred← citeshttps://doi.org/10.1145/371282.371364openalex-snapshot
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
inferred← citeshttps://doi.org/10.23919/date.2018.8341979openalex-snapshot
Symbolic quick error detection using symbolic initial state for pre-silicon verification
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116515openalex-snapshot
Gap-free Processor Verification by S2QED and Property Generation
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