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Design and verification of regular synchronous circuits
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-15975-4_39openalex-snapshot
Designing regular array architectures using higher order functions
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_24openalex-snapshot
A Mathematical Approach to Modelling the Flow of Data and Control in Computational Networks
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_25openalex-snapshot
A Wavefront Notation Tool for VLSI Array Design
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1184/r1/6608831openalex-snapshot
Reasoning about synchronous systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-15975-4_39openalex-snapshot
Designing regular array architectures using higher order functions
inferred← citeshttps://doi.org/10.1007/978-1-4471-3166-3_6openalex-snapshot
Deriving the fast Fourier algorithm by calculation
inferred← citeshttps://doi.org/10.1007/978-1-4615-3556-0_2openalex-snapshot
Formal Hardware Verification Methods: A Survey
inferred← citeshttps://doi.org/10.1007/978-1-4684-5511-3_14openalex-snapshot
Timeless Truths about Sequential Circuits
inferred← citeshttps://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferred← citeshttps://doi.org/10.1016/0165-6074(88)90081-6openalex-snapshot
Formal specification and verification of microprocessor systems
inferred← citeshttps://doi.org/10.1016/0165-6074(89)90041-0openalex-snapshot
Systolic array description in F2
inferred← citeshttps://doi.org/10.1016/0167-9260(89)90004-7openalex-snapshot
Formal specification and verification of microprocessor systems
inferred← citeshttps://doi.org/10.1049/el:19870816openalex-snapshot
Systolic arrays for recursive digital filtering
inferred← citeshttps://doi.org/10.1109/31.1864openalex-snapshot
Comments on "An improved sufficient condition for absence of limit cycles in digital filters
inferred← citeshttps://doi.org/10.1109/iccd.1988.25769openalex-snapshot
A functional approach to formal hardware verification: the MTI experience
inferred← citeshttps://doi.org/10.1109/icvd.1993.669671openalex-snapshot
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
inferred← citeshttps://doi.org/10.48456/tr-201openalex-snapshot
Formalizing abstraction mechanisms for hardware verification in higher order logic
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