On the public citation graph
The evolution of instruction sequencing
0 signed · 26 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.48865openalex-snapshot
Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
inferredcites →https://doi.org/10.1109/2.68openalex-snapshot
Reducing the branch penalty in pipelined processors
inferredcites →https://doi.org/10.1109/t-c.1972.223514openalex-snapshot
The Inhibition of Potential Parallelism by Conditional Jumps
inferredcites →https://doi.org/10.1145/30350.30385openalex-snapshot
The hardware architecture of the CRISP microprocessor
inferredcites →https://doi.org/10.1145/633625.52433openalex-snapshot
Performance tradeoffs in cache design
inferredcites →https://doi.org/10.1145/68182.68200openalex-snapshot
Program optimization for instruction caches
inferredcites →https://doi.org/10.1145/68182.68209openalex-snapshot
Limits on multiple instruction issue
inferredcites →https://doi.org/10.1145/70082.68200openalex-snapshot
Program optimization for instruction caches
inferredcites →https://doi.org/10.1145/70082.68209openalex-snapshot
Limits on multiple instruction issue
inferredcites →https://doi.org/10.1145/77254.77263openalex-snapshot
The case for the sustained performance computer architecture
inferredcites →https://doi.org/10.1145/800050.801820openalex-snapshot
Hardware/software tradeoffs for increased performance
inferredcites →https://doi.org/10.1147/rd.111.0008openalex-snapshot
The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling
inferredcites →https://doi.org/10.1147/rd.341.0037openalex-snapshot
Machine organization of the IBM RISC System/6000 processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/bf00155803openalex-snapshot
An introduction to compilation issues for parallel machines
inferred← citeshttps://doi.org/10.1109/40.296166openalex-snapshot
Predicting and precluding problems with memory latency
inferred← citeshttps://doi.org/10.1109/pccc.1995.472454openalex-snapshot
HyperPascal for architecture independent parallel programming
inferred← citeshttps://doi.org/10.1109/secon.1995.513061openalex-snapshot
HyperPascal-an architecture independent Pascal interface for parallel programming
inferred← citeshttps://doi.org/10.1145/139669.139681openalex-snapshot
Effects of building blocks on the performance of super-scalar architecture
inferred← citeshttps://doi.org/10.1145/146628.139681openalex-snapshot
Effects of building blocks on the performance of super-scalar architecture
inferred← citeshttps://doi.org/10.1145/152479.152481openalex-snapshot
Extraction of massive instruction level parallelism
inferred← citeshttps://doi.org/10.1145/152835.152836openalex-snapshot
Extraction of massive instruction level parallelism
inferred← citeshttps://doi.org/10.1201/9781420036503.ch1openalex-snapshot
History of Low-Power Electronics
inferred← citeshttps://doi.org/10.4995/thesis/10251/55328openalex-snapshot
Utilización de memorias cache con bloqueo en sistemas de tiempo real.
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