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A novel ASIC design approach based on a new machine paradigm

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/cmpeur.1989.93471openalex-snapshot
MOM-map-oriented machine-a partly custom-designed architecture compared to standard hardware
inferredcites →https://doi.org/10.1109/dac.1982.1585574openalex-snapshot
A Deterministic Finite Automaton Approach to Design Rule Checking for VLSI
inferredcites →https://doi.org/10.1109/tec.1961.5219222openalex-snapshot
An Algorithm for Path Connections and Its Applications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Morphware and Configware
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Novel high performance machine paradigms and fast-turnaround ASIC design methods: A consequence of, and, a challenge to, field-programmable logic
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A new FPGA architecture for word-oriented datapaths
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Classification and performance of reconfigurable architectures
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The Java Environment for Reconfigurable Computing
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CGRA Background and Related Work
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Concept of the Blocks Architecture
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CGRA-Hintergrund und verwandte Arbeiten
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Konzept der Blocks-Architektur
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Configware and morphware going mainstream
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The flexibility of configurable computing
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A reconfigurable data-driven ALU for Xputers
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Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency
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A two-level co-design framework for Xputer-based data-driven reconfigurable accelerators
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MLMap: A Multilevel Mapping Flow for Coarse Grained Reconfigurable Architecture
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Are we really ready for the breakthrough? [morphware]
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FPGA computer architectures
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Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
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Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling
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Streaming Elements for FPGA Signal and Image Processing Accelerators
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A datapath synthesis system for the reconfigurable datapath architecture
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A Survey of Coarse-Grained Reconfigurable Architecture and Design
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HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics
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Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane
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A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing
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Coarse grain reconfigurable architecture (embedded tutorial)
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The digital divide of computing
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Coarse-Grained Reconfigurable Computing with the Versat Architecture
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A decade of reconfigurable computing: a visionary retrospective
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Stream-Based Computing and Future Television
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Stream-Based Computing and Future Television
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Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures
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