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A Survey of Coarse-Grained Reconfigurable Architecture and Design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
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Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
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Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
inferredcites →https://doi.org/10.1016/b978-012370522-8.50007-8openalex-snapshot
Reconfigurable Computing Systems
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A holistic approach for tightly coupled reconfigurable parallel processors
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Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
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PACT XPP—A Self-Reconfigurable Data Processing Architecture
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Temporal correlation detection using computational phase-change memory
inferredcites →https://doi.org/10.1049/ip-cdt:20045086openalex-snapshot
Reconfigurable computing: architectures and design methods
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A Survey on Dynamically Reconfigurable Processors
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Executing a program on the MIT tagged-token dataflow architecture
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MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
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Baring it all to software: Raw machines
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PipeRench: a reconfigurable architecture and compiler
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A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths
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A novel ASIC design approach based on a new machine paradigm
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Proceedings of the IEEE 2008 custom integrated circuits conference
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Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
inferredcites →https://doi.org/10.1109/date.2001.915091openalex-snapshot
A decade of reconfigurable computing: a visionary retrospective
inferredcites →https://doi.org/10.1109/ddecs.2008.4538762openalex-snapshot
Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform
inferredcites →https://doi.org/10.1109/fpt.2004.1393261openalex-snapshot
Stream applications on the dynamically reconfigurable processor
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Proceedings 2007 International Conference on Field Programmable Technology
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Proceedings 2008 international conference on embedded computer systems: Architectures, modeling and simulation
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Proceedings of 21 International Symposium on Computer Architecture
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1.1 Computing's energy problem (and what we can do about it)
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Cramming More Components Onto Integrated Circuits
inferredcites →https://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferredcites →https://doi.org/10.1109/jproc.2014.2387696openalex-snapshot
Fundamental Underpinnings of Reconfigurable Computing Architectures
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Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
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i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing
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Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
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GPUs and the Future of Parallel Computing
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Dark Silicon and the End of Multicore Scaling
inferredcites →https://doi.org/10.1109/mm.2012.51openalex-snapshot
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
inferredcites →https://doi.org/10.1109/mm.2014.55openalex-snapshot
Near-Data Processing: Insights from a MICRO-46 Workshop
inferredcites →https://doi.org/10.1109/mm.2015.42openalex-snapshot
A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
inferredcites →https://doi.org/10.1109/tc.1972.5009071openalex-snapshot
Some Computer Organizations and Their Effectiveness
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2017.2729340openalex-snapshot
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures
inferredcites →https://doi.org/10.1109/tcsii.2017.2728814openalex-snapshot
HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing
inferredcites →https://doi.org/10.1109/tifs.2016.2518130openalex-snapshot
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture
inferredcites →https://doi.org/10.1109/tifs.2016.2612638openalex-snapshot
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks
inferredcites →https://doi.org/10.1109/tmm.2015.2463735openalex-snapshot
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding
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An instruction-level distributed processor for symmetric-key cryptography
inferredcites →https://doi.org/10.1109/tvlsi.2007.912133openalex-snapshot
The Reconfigurable Instruction Cell Array
inferredcites →https://doi.org/10.1109/tvlsi.2008.2006846openalex-snapshot
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/tvlsi.2009.2025280openalex-snapshot
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/tvlsi.2012.2228015openalex-snapshot
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/tvlsi.2017.2688340openalex-snapshot
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
inferredcites →https://doi.org/10.1145/1749603.1749604openalex-snapshot
Compiling for reconfigurable computing
inferredcites →https://doi.org/10.1145/225830.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors
inferredcites →https://doi.org/10.1145/2540708openalex-snapshot
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
inferredcites →https://doi.org/10.1145/2638558openalex-snapshot
A Software Scheme for Multithreading on CGRAs
inferredcites →https://doi.org/10.1145/2676726.2677002openalex-snapshot
Tractable Refinement Checking for Concurrent Objects
inferredcites →https://doi.org/10.1145/2872362.2872415openalex-snapshot
Generating Configurable Hardware from Parallel Patterns
inferredcites →https://doi.org/10.1145/2872887.2750386openalex-snapshot
A scalable processing-in-memory accelerator for parallel graph processing
inferredcites →https://doi.org/10.1145/288548openalex-snapshot
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98
inferredcites →https://doi.org/10.1145/2954679.2872415openalex-snapshot
Generating Configurable Hardware from Parallel Patterns
inferredcites →https://doi.org/10.1145/3079856openalex-snapshot
Proceedings of the 44th Annual International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/359576.359585openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.1145/641675.642111openalex-snapshot
A preliminary architecture for a basic data-flow processor
inferredcites →https://doi.org/10.1145/800145openalex-snapshot
Proceedings of the 9th annual workshop on Microprogramming - MICRO 9
inferredcites →https://doi.org/10.1155/2013/683615openalex-snapshot
Ingredients of Adaptability: A Survey of Reconfigurable Processors
inferredcites →https://doi.org/10.1155/2016/2478907openalex-snapshot
Operating System Concepts for Reconfigurable Computing: Review and Survey
inferredcites →https://doi.org/10.24251/hicss.2023.000openalex-snapshot
Proceedings of the 56th Hawaii International Conference on System Sciences
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A design flow for architecture exploration and implementation of partially reconfigurable processors
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Heterogeneous reconfigurable architectures for machine learning dataflows
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Fast DSE of reconfigurable accelerator systems via ensemble machine learning
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Automating functional unit and register binding for synchoros CGRA platform
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UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment
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Energy Efficient Hardware Loop Based Optimization for CGRAs
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Survey of Coarse-Grained Reconfigurable Architectures Mapping Algorithms
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Application-specific FPGAs: cryptographic agility through customized reconfigurable architectures
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A Scalable Mapping Method for Elastic CGRAs
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A Power-Centric Methodology to Characterize Edge AI SoC with Limited Telemetry Capabilities
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Compiler-Based Performance Results for Regular Application Kernels on the HPC CGRA HiPReP
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Control-Flow Execution on CGRAs: A Comprehensive Survey of Architectural and Compilation Techniques
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SARA: Scaling a Reconfigurable Dataflow Accelerator
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Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶
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DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays
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A RISC-V Heterogeneous SoC and Its Co-Scheduling Optimization Approach for Digital Signal Processing
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THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE
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Deep Learning-Assisted Video Compression Framework
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RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays
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BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge
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A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation
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MOE: An Efficient Multicasting and One-hot Encoding Hybrid Configuration Compression Technique for CGRAs
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A 22nm Reconfigurable Systolic Array for FFT and AI Inference
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Reuse-Aware Partitioning of Dataflow Graphs on a Tightly-Coupled CGRA
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MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator
inferred← citeshttps://doi.org/10.1109/isvlsi59464.2023.10238676openalex-snapshot
X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model
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A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications
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A Survey on Stream-Based Architectures: From Accelerators to CPUs
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Field Programmable Neural Array for Biomedical Signal Processing
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A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration
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Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET
inferred← citeshttps://doi.org/10.1109/lascas67804.2026.11457151openalex-snapshot
Energy-Efficient Mappings in the Athena CGRA
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Wafer-Scale Computing: Advancements, Challenges, and Future Perspectives [Feature]
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An Overview of Challenges and Requirements for Real-Time Spectrum Sensing in Modern RF Autonomy Systems
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Synthesis Method for CGRA Processors based on Imitation Model
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Multi-Operating System and Multi-Database Detection Based on Multi-Agent Reinforcement Learning in a Distributed Environment
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00080openalex-snapshot
Generalizing Ray Tracing Accelerators for Tree Traversals on GPUs
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00099openalex-snapshot
ICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00100openalex-snapshot
SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
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A Binary Translation Framework for Automated Hardware Generation
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Review and Evaluation of End-to-End Video Compression with Deep-Learning
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An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability
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Comparative Sentiment Analysis of Cryptocurrency Apps Using BERT, RoBERTa, and ChatGPT
inferred← citeshttps://doi.org/10.1109/ojcas.2024.3518110openalex-snapshot
Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability
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Mapping YOLOv4-Tiny on FPGA-Based DNN Accelerator by Using Dynamic Fixed-Point Method
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ILP Based Mapping for Elastic CGRAs
inferred← citeshttps://doi.org/10.1109/sbac-pad66369.2025.00013openalex-snapshot
MIDAS: A Mapping Infrastructure for Configurable, Data-Streaming Based Domain Specific Accelerators
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A Management Technique for Concurrent Access to a Reconfigurable Accelerator
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Evaluating the Performance, Energy and Area Tradeoffs of ATHENA in Superscalar Processors
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A Simulation Methodology for Transparent Coarse-Grained Reconfigurable Architectures
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A Multi-Domain Architectural Efficiency Metric
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Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors
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Resilient and Secure Programmable System-on-Chip Accelerator Offload
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ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design
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TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs
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Morphling: A Reconfigurable Architecture for Tensor Computation
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Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning
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M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2024.3383349openalex-snapshot
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge
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Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations
inferred← citeshttps://doi.org/10.1109/tcad.2024.3520024openalex-snapshot
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration
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DynMap: A Heuristic Dynamic Mapper for CGRA Multitask Dynamic Resource Allocation
inferred← citeshttps://doi.org/10.1109/tcad.2025.3572343openalex-snapshot
EDWAC: A Deadlock-Free Scheme for Compiling Whole Programs Onto Dynamically Reconfigurable Dataflow Architectures
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MultiSky: Dynamic Resource Allocation Framework for High-Throughput CGRA Multitask Execution
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Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation
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Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips
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CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs
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Raccoon: Lightweight Support for Comprehensive Control Flows in Reconfigurable Spatial Architectures
inferred← citeshttps://doi.org/10.1109/tpds.2025.3604815openalex-snapshot
PreTrans: Enabling Efficient CGRA Multi-Task Context Switch Through Config Pre-Mapping and Data Transceiving
inferred← citeshttps://doi.org/10.1109/tpds.2026.3722842openalex-snapshot
RedPanda: A Unified Compilation Framework for Dataflow-Based CGRAs and High-Level Synthesis
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A Dynamic General Accelerator for Integer and Fixed-Point Processing
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HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3697086openalex-snapshot
Toward Efficient Edge AI With Heterogeneous Computing and Multilevel Optimization
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SAT-Based Data-Flow Mapping Onto Array Processor
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RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1142/s0218126623501578openalex-snapshot
DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture
inferred← citeshttps://doi.org/10.1142/s0218126625503050openalex-snapshot
ASFRM: An Array State Self-feedback-Based Self-reconfiguration Mechanism in a Reconfigurable Array Processor
inferred← citeshttps://doi.org/10.1142/s0218126626500970openalex-snapshot
Configuration Information Generation for Reconfigurable Decoupled Access-Execute CGRA
inferred← citeshttps://doi.org/10.1145/3394885.3431414openalex-snapshot
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs
inferred← citeshttps://doi.org/10.1145/3437378.3444365openalex-snapshot
A Traffic and Resource Aware Online Storm Scheduler
inferred← citeshttps://doi.org/10.1145/3456172.3456196openalex-snapshot
Strategies for Heterogeneous Multi-Core Processing Based on Graph Programming
inferred← citeshttps://doi.org/10.1145/3458471openalex-snapshot
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation
inferred← citeshttps://doi.org/10.1145/3466752.3480134openalex-snapshot
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator
inferred← citeshttps://doi.org/10.1145/3483237openalex-snapshot
Component-based Analysis of Dynamic Search Performance
inferred← citeshttps://doi.org/10.1145/3503161.3547928openalex-snapshot
Consistency-Contrast Learning for Conceptual Coding
inferred← citeshttps://doi.org/10.1145/3503222.3507772openalex-snapshot
REVAMP: a systematic framework for heterogeneous CGRA realization
inferred← citeshttps://doi.org/10.1145/3531062openalex-snapshot
Advantages of a Statistical Estimation Approach for Clock Frequency Estimation of Heterogeneous and Irregular CGRAs
inferred← citeshttps://doi.org/10.1145/3532989openalex-snapshot
Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs
inferred← citeshttps://doi.org/10.1145/3543544openalex-snapshot
Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator
inferred← citeshttps://doi.org/10.1145/3544971openalex-snapshot
Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator
inferred← citeshttps://doi.org/10.1145/3550071openalex-snapshot
An Efficient and Flexible Stochastic CGRA Mapping Approach
inferred← citeshttps://doi.org/10.1145/3563946openalex-snapshot
Domain-Specific Architectures: Research Problems and Promising Approaches
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MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search
inferred← citeshttps://doi.org/10.1145/3579371.3589084openalex-snapshot
MESA: Microarchitecture Extensions for Spatial Architecture Generation
inferred← citeshttps://doi.org/10.1145/3630007openalex-snapshot
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing
inferred← citeshttps://doi.org/10.1145/3631118openalex-snapshot
Flip : Data-centric Edge CGRA Accelerator
inferred← citeshttps://doi.org/10.1145/3637543.3652876openalex-snapshot
Open-Source Elastic CGRA Generator
inferred← citeshttps://doi.org/10.1145/3649329.3658269openalex-snapshot
CLUMAP: Clustered Mapper for CGRAs with Predication
inferred← citeshttps://doi.org/10.1145/3656642openalex-snapshot
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
inferred← citeshttps://doi.org/10.1145/3676641.3716013openalex-snapshot
PICACHU: Plug-In CGRA Handling Upcoming Nonlinear Operations in LLMs
inferred← citeshttps://doi.org/10.1145/3689729openalex-snapshot
FlowCert: Translation Validation for Asynchronous Dataflow via Dynamic Fractional Permissions
inferred← citeshttps://doi.org/10.1145/3699514openalex-snapshot
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing
inferred← citeshttps://doi.org/10.1145/3712031.3712328openalex-snapshot
Lossy Compressed Collective Inter-FPGA Communications
inferred← citeshttps://doi.org/10.1145/3721294openalex-snapshot
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
inferred← citeshttps://doi.org/10.1145/3723045openalex-snapshot
PRISA: A Potential Region-based Intelligent Search Algorithm for Dataflow Graph Mapping in Spatial CGRAs
inferred← citeshttps://doi.org/10.1145/3725843.3756019openalex-snapshot
FexMo: Enabling Fuse Execution Mode for Multi-task CGRAs
inferred← citeshttps://doi.org/10.1145/3725843.3756126openalex-snapshot
Misam: Machine Learning Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication
inferred← citeshttps://doi.org/10.1145/3728179.3728196openalex-snapshot
Systolic Array-Based Matrix Multiplication and Reduction on Elastic CGRAs
inferred← citeshttps://doi.org/10.1145/3729215openalex-snapshot
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
inferred← citeshttps://doi.org/10.1145/3733721openalex-snapshot
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
inferred← citeshttps://doi.org/10.1145/3746027.3755059openalex-snapshot
Neural Video Compression with In-Loop Contextual Filtering and Out-of-Loop Reconstruction Enhancement
inferred← citeshttps://doi.org/10.1145/3765623openalex-snapshot
Adaptive Computing in Memory Meets Conventional Batteryless Platforms
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