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Reconfigurable pipelined 2-D convolvers for fast digital signal processing

https://doi.org/10.1109/92.784091
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inferredcites →https://doi.org/10.1007/3-540-57091-8_40openalex-snapshot
Chameleon: A workstation of a different colour
inferredcites →https://doi.org/10.1016/1049-9660(92)90019-yopenalex-snapshot
Digital image processing (2nd ed.)
inferredcites →https://doi.org/10.1016/b978-0-12-628980-0.50008-1openalex-snapshot
Digital Image Processing
inferredcites →https://doi.org/10.1080/00207219308907150openalex-snapshot
A programmable image processing system using FPGAs
inferredcites →https://doi.org/10.1109/54.232470openalex-snapshot
Hardware-software cosynthesis for digital systems
inferredcites →https://doi.org/10.1109/92.784091openalex-snapshot
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
inferredcites →https://doi.org/10.1109/iccd.1991.139928openalex-snapshot
An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration
inferredcites →https://doi.org/10.1109/iscas.1994.409222openalex-snapshot
Virtual hardware and the limits of computational speed-up
inferredcites →https://doi.org/10.1109/naecon.1993.290896openalex-snapshot
Realization of a dynamically reconfigurable preprocessor
inferredcites →https://doi.org/10.1109/proc.1979.11331openalex-snapshot
Basics of cellular logic with some applications in medical image processing
inferredcites →https://doi.org/10.1117/12.960445openalex-snapshot
A 2-D Convolver Architecture For Real-Time Image Processing
inferredcites →https://doi.org/10.1117/12.968988openalex-snapshot
A High Performance Convolution Processor
inferredcites →https://doi.org/10.1117/12.970119openalex-snapshot
A 2-D Convolver Architecture For Real-Time Image Processing

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inferred← citeshttps://doi.org/10.1007/11572961_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-1-84800-304-0_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-98347-5_1openalex-snapshot
Approximate Arithmetic Circuits: Design and Applications
inferred← citeshttps://doi.org/10.1007/978-3-031-21514-8_42openalex-snapshot
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture
inferred← citeshttps://doi.org/10.1007/978-3-319-56258-2_22openalex-snapshot
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms
inferred← citeshttps://doi.org/10.1007/978-3-540-74309-5_22openalex-snapshot
A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels
inferred← citeshttps://doi.org/10.1007/978-981-15-0426-6_18openalex-snapshot
Area-Efficient Splitting Mechanism for 2D Convolution on FPGA
inferred← citeshttps://doi.org/10.1007/s00034-019-01083-4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10470-023-02208-1openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11042-011-0906-yopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11042-023-16472-wopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11227-021-03963-6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11227-023-05377-yopenalex-snapshot
Real-time approximate and combined 2D convolvers for FPGA-based image processing
inferred← citeshttps://doi.org/10.1007/s11265-015-1056-7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11277-020-07994-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11554-011-0201-1openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11554-017-0690-7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11554-023-01339-yopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s44444-025-00085-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.compmedimag.2008.11.001openalex-snapshot
X-ray angiogram images enhancement by facet-based adaptive anisotropic diffusion
inferred← citeshttps://doi.org/10.1016/j.future.2022.10.001openalex-snapshot
ANNA: Accelerating Neural Network Accelerator through software-hardware co-design for vertical applications in edge systems
inferred← citeshttps://doi.org/10.1016/j.ijleo.2013.04.046openalex-snapshot
Perceptual contrast enhancement with dynamic range adjustment
inferred← citeshttps://doi.org/10.1016/j.measurement.2004.09.007openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.mejo.2010.08.008openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2004.10.004openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2006.02.016openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2006.07.004openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102852openalex-snapshot
Efficient separable convolution using field programmable gate arrays
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103351openalex-snapshot
A hybrid precision low power computing-in-memory architecture for neural networks
inferred← citeshttps://doi.org/10.1016/j.patrec.2004.09.003openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.rti.2004.06.001openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.sysarc.2012.06.002openalex-snapshot
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
inferred← citeshttps://doi.org/10.1016/j.vlsi.2006.07.001openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.10.012openalex-snapshot
A high-performance convolution block oriented accelerator for MBConv-Based CNNs
inferred← citeshttps://doi.org/10.1023/a:1011196613858openalex-snapshot
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems
inferred← citeshttps://doi.org/10.1023/b:vlsi.0000028534.35761.a8openalex-snapshot
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing
inferred← citeshttps://doi.org/10.1080/1206212x.2008.11441909openalex-snapshot
A High Performance Architecture for Implementation of 2-D Convolution with Quadrant Symmetric Kernels
inferred← citeshttps://doi.org/10.1088/1402-4896/ae8be3openalex-snapshot
Implementations of a novel approximate architecture for 2D convolution for image processing applications
inferred← citeshttps://doi.org/10.1109/30.826397openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/access.2018.2890150openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/access.2020.3025344openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/aicas48895.2020.9073835openalex-snapshot
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization
inferred← citeshttps://doi.org/10.1109/apccas.2006.342541openalex-snapshot
A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels
inferred← citeshttps://doi.org/10.1109/asicon.2017.8252623openalex-snapshot
Efficient fast convolution architectures for convolutional neural network
inferred← citeshttps://doi.org/10.1109/bigdata47090.2019.9006494openalex-snapshot
Exploration of OpenCL 2D Convolution Kernels on Intel FPGA, CPU, and GPU Platforms
inferred← citeshttps://doi.org/10.1109/cac53003.2021.9728699openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/camp.2003.1598171openalex-snapshot
Multiscale Image Representation Based on Gabor Transform Using Reconfigurable FPGA
inferred← citeshttps://doi.org/10.1109/comptelix.2017.8003992openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/dft.2016.7684065openalex-snapshot
Design and analysis of an approximate 2D convolver
inferred← citeshttps://doi.org/10.1109/dsd.2006.16openalex-snapshot
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing
inferred← citeshttps://doi.org/10.1109/fccm.2006.13openalex-snapshot
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing
inferred← citeshttps://doi.org/10.1109/fpl.2005.1515789openalex-snapshot
Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing
inferred← citeshttps://doi.org/10.1109/fpt.2017.8280163openalex-snapshot
All binarized convolutional neural network and its implementation on an FPGA
inferred← citeshttps://doi.org/10.1109/icacci.2015.7275656openalex-snapshot
Network on chip based multi-function image processing system using FPGA
inferred← citeshttps://doi.org/10.1109/icacci.2016.7732339openalex-snapshot
Using FPGA-SoC interface for low cost IoT based image processing
inferred← citeshttps://doi.org/10.1109/icccnt56998.2023.10308081openalex-snapshot
A Novel approach for Image Processing based on colluding of Raspberry-Pi and FPGA adopting IoT
inferred← citeshttps://doi.org/10.1109/icce-taiwan49838.2020.9258026openalex-snapshot
Low-Power Small-Area $3\times 3$ Convolution Hardware Design
inferred← citeshttps://doi.org/10.1109/icecs.2001.957581openalex-snapshot
A reconfigurable 2D convolver for real-time SAR imaging
inferred← citeshttps://doi.org/10.1109/icecs.2006.379826openalex-snapshot
Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution
inferred← citeshttps://doi.org/10.1109/icecs46596.2019.8964670openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icicm54364.2021.9660324openalex-snapshot
A More Scalable Deep-learning Processing Unit For Depthwise Separable Convolution
inferred← citeshttps://doi.org/10.1109/iciea.2009.5138287openalex-snapshot
Neighborhood dependent approach for low power 2D convolution in video processing applications
inferred← citeshttps://doi.org/10.1109/icip.2003.1246749openalex-snapshot
Embedded co-processor architecture for CMOS based image acquisition
inferred← citeshttps://doi.org/10.1109/icta53157.2021.9661886openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icta56932.2022.9963056openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icvris.2019.00089openalex-snapshot
A DSP48-Based Reconfigurable 2-D Convolver on FPGA
inferred← citeshttps://doi.org/10.1109/idt.2011.6123108openalex-snapshot
An area-efficient 2-D convolution implementation on FPGA for space applications
inferred← citeshttps://doi.org/10.1109/iecon.2005.1568933openalex-snapshot
Fast 3D reconstruction for small autonomous robots
inferred← citeshttps://doi.org/10.1109/igcc.2014.7039144openalex-snapshot
High level performance model based design space exploration for energy-efficient designs on FPGAs
inferred← citeshttps://doi.org/10.1109/igcc.2014.7039182openalex-snapshot
Energy-efficient parameterized 2-D separable convolution on FPGA
inferred← citeshttps://doi.org/10.1109/iscas.2002.1011463openalex-snapshot
Residue number system reconfigurable datapath
inferred← citeshttps://doi.org/10.1109/iscas.2018.8351080openalex-snapshot
Design and Application of an Approximate 2-D Convolver with Error Compensation
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10182079openalex-snapshot
System on Chip Testbed for Deep Neuromorphic Neural Networks
inferred← citeshttps://doi.org/10.1109/ismvl.2019.00023openalex-snapshot
Noise Convolutional Neural Networks and FPGA Implementation
inferred← citeshttps://doi.org/10.1109/isscs.2007.4292788openalex-snapshot
Adaptable Area-Efficient Parallel Architecture for Grey and Color Image Convolvers
inferred← citeshttps://doi.org/10.1109/isvlsi.2005.15openalex-snapshot
An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels
inferred← citeshttps://doi.org/10.1109/isvlsi.2016.129openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware
inferred← citeshttps://doi.org/10.1109/itng.2009.287openalex-snapshot
Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications
inferred← citeshttps://doi.org/10.1109/mwscas.2014.6908411openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mysurucon55714.2022.9972491openalex-snapshot
Area Reduction in Field Programmable Gate Array with Convolutional Neural Network
inferred← citeshttps://doi.org/10.1109/reconfig.2005.20openalex-snapshot
FPGA-Based Customizable Systolic Architecture for Image Processing Applications
inferred← citeshttps://doi.org/10.1109/sbcci.2000.876043openalex-snapshot
Design of a classification system for rectangular shapes using a co-design environment
inferred← citeshttps://doi.org/10.1109/sips.2005.1579866openalex-snapshot
Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing
inferred← citeshttps://doi.org/10.1109/sitis.2007.32openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tcad.2017.2705069openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2019.2917852openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tce.2008.4711272openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tcsi.2024.3525418openalex-snapshot
A Low-Latency Feed-Forward Architecture for Image Filtering via Row-by-Row Processing
inferred← citeshttps://doi.org/10.1109/tcsii.2005.857091openalex-snapshot
Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing
inferred← citeshttps://doi.org/10.1109/tcsii.2006.886898openalex-snapshot
A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers
inferred← citeshttps://doi.org/10.1109/tcsii.2016.2536202openalex-snapshot
Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing
inferred← citeshttps://doi.org/10.1109/tcsii.2018.2832064openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tcsvt.2011.2162760openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tencon.2000.892259openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tencon.2007.4428941openalex-snapshot
Generic 2-D gaussian smoothing filter for noisy image processing
inferred← citeshttps://doi.org/10.1109/tencon.2008.4766488openalex-snapshot
A fast and area efficient 2-D convolver for real time image processing
inferred← citeshttps://doi.org/10.1109/tetc.2016.2601220openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tie.2010.2040556openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tmscs.2017.2695588openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tnb.2017.2705104openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tvlsi.2003.812306openalex-snapshot
Mapping of generalized template matching onto reconfigurable computers
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2170204openalex-snapshot
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2815603openalex-snapshot
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inferred← citeshttps://doi.org/10.1117/1.1794705openalex-snapshot
Facet-based star acquisition method
inferred← citeshttps://doi.org/10.1117/1.2710469openalex-snapshot
New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets
inferred← citeshttps://doi.org/10.1117/12.767125openalex-snapshot
An architecture for on-the-fly correction of radial distortion using FPGA
inferred← citeshttps://doi.org/10.1117/12.781058openalex-snapshot
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inferred← citeshttps://doi.org/10.1142/s0218126617501882openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2490830openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2847263.2847265openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3007652openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3020078.3021698openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3020078.3021727openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3079758openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3174243.3174266openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3241793.3241803openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3241793.3241814openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3274694.3274696openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3597031.3597049openalex-snapshot
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inferred← citeshttps://doi.org/10.1155/2008/597872openalex-snapshot
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inferred← citeshttps://doi.org/10.1155/asp.2005.1024openalex-snapshot
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inferred← citeshttps://doi.org/10.1371/journal.pone.0166056openalex-snapshot
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inferred← citeshttps://doi.org/10.1587/transinf.2018rcp0005openalex-snapshot
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inferred← citeshttps://doi.org/10.1587/transinf.2022pap0004openalex-snapshot
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inferred← citeshttps://doi.org/10.17760/d20385564openalex-snapshot
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inferred← citeshttps://doi.org/10.18280/ria.350610openalex-snapshot
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inferred← citeshttps://doi.org/10.28948/ngumuh.522790openalex-snapshot
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inferred← citeshttps://doi.org/10.3233/978-1-60750-692-8-152openalex-snapshot
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inferred← citeshttps://doi.org/10.32657/10356/2379openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/electronics14030582openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/jlpea10040036openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/s21155081openalex-snapshot
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inferred← citeshttps://doi.org/10.3929/ethz-a-004717340openalex-snapshot
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inferred← citeshttps://doi.org/10.4304/jcp.8.6.1411-1416openalex-snapshot
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inferred← citeshttps://doi.org/10.4316/aece.2015.01014openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1803.05847openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/2755753.2755910openalex-snapshot
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inferred← citeshttps://doi.org/10.5753/wscad_estendido.2006.18968openalex-snapshot
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inferred← citeshttps://doi.org/10.5772/30186openalex-snapshot
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