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Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.506424openalex-snapshot
Analysis and implementation of hybrid switching
inferredcites →https://doi.org/10.1109/12.53599openalex-snapshot
Performance analysis of k-ary n-cube interconnection networks
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/date.2003.1253632openalex-snapshot
Packetized on-chip interconnect communication analysis for MPSoC
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm
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CRMPSoC: New Solution for Feasible Reconfigurable MPSoC
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A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
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A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
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ReNo: novel switch architecture for reliability improvement of NoCs
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SDNoC: Software defined network on a chip
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Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
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A high-performance, low-area reconfiguration controller for network-on-chip-based partial dynamically reconfigurable system-on-chip designs
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New Automatic Agent-Based Solutions for Feasible Reconfigurable MP-SoC Architectures
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Dynamically Reconfigurable NoC with Bus Based Interface for Ease of Integration and Reduced Design Time
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R3TOS: A reliable reconfigurable real-time operating system
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Formal methodology for modeling, verifying and optimizing reconfigurable NoC modes
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Prototyping of a Network-on-Chip on Spartan 3E FPGA
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Analytical performance analysis of mesh network-on-chip based on network calculus
inferred← citeshttps://doi.org/10.1109/compsac.2016.218openalex-snapshot
Verification of Reconfigurable NoC under Quality of Service Constraints
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Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip
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A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
inferred← citeshttps://doi.org/10.1109/em-com.2009.5402995openalex-snapshot
PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/etncc.2015.7184805openalex-snapshot
Towards better communication in adaptive system-on-chip for multicore architectures
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An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
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Round-based priority arbitration for predictable and reconfigurable Network-on-Chip
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412142openalex-snapshot
Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor
inferred← citeshttps://doi.org/10.1109/hpcs.2010.5547088openalex-snapshot
Towards a bio-inspired architecture for autonomic network-on-chip
inferred← citeshttps://doi.org/10.1109/hpcsim.2012.6266925openalex-snapshot
Performance evaluation of a flow control algorithm for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357093openalex-snapshot
DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube
inferred← citeshttps://doi.org/10.1109/icis.2015.7166664openalex-snapshot
Petri Nets-based design of real-time reconfigurable networks on chips
inferred← citeshttps://doi.org/10.1109/idt.2008.4802459openalex-snapshot
A combined packet and circuit switching routing algorithm for networks-on-chips
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536514openalex-snapshot
Implementation of a reconfigurable data protection module for NoC-based MPSoCs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470728openalex-snapshot
Stack protection unit as a step towards securing MPSoCs
inferred← citeshttps://doi.org/10.1109/ispa.2011.40openalex-snapshot
A Flexible High Speed Star Network Based on Peer to Peer Links on FPGA
inferred← citeshttps://doi.org/10.1109/reconfig.2011.52openalex-snapshot
Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration
inferred← citeshttps://doi.org/10.1109/reconfig.2012.6416726openalex-snapshot
Adapting communication for adaptable processors: A multi-axis reconfiguration approach
inferred← citeshttps://doi.org/10.1109/rsp.2008.31openalex-snapshot
An Automated Design Flow for NoC-based MPSoCs on FPGA
inferred← citeshttps://doi.org/10.1109/samos.2011.6045468openalex-snapshot
On-chip network resource management design and validation
inferred← citeshttps://doi.org/10.1109/tc.2012.123openalex-snapshot
Differentiated Communication Services for NoC-Based MPSoCs
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2278334openalex-snapshot
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip
inferred← citeshttps://doi.org/10.1109/vlsid.2019.00119openalex-snapshot
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
inferred← citeshttps://doi.org/10.1109/wccais.2014.6916634openalex-snapshot
Mathematical performance evaluation of mesh Network-on-Chip for VBR flow
inferred← citeshttps://doi.org/10.1145/1868433.1868441openalex-snapshot
Hierarchical multi-agent protection system for NoC based MPSoCs
inferred← citeshttps://doi.org/10.1145/1873548.1873560openalex-snapshot
Enhancing network-on-chip components to support security of processing elements
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Concurrent hybrid switching for massively parallel systems-on-chip
inferred← citeshttps://doi.org/10.1145/2460216.2460222openalex-snapshot
A low overhead abstract architecture for FPGA resource management
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Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration
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Network-on-Chip: The Next Generation of System-on-Chip Integration
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Reconfigurable Network-on-Chip Design
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Reconfigurable Network-on-Chip Design
inferred← citeshttps://doi.org/10.14569/ijacsa.2017.081139openalex-snapshot
FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC
inferred← citeshttps://doi.org/10.21474/ijar01/7003openalex-snapshot
DESIGN AND IMPLEMENTATION OF NOVEL NOC ARCHITECTURE ON FPGA.
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A Survey on Reconfigurable System-on-Chips
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Performance Analysis of an Efficient Router using X Y Algorithm
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Adaptive Network-on-Chip
inferred← citeshttps://doi.org/10.4018/978-1-5225-2255-3.ch395openalex-snapshot
Adaptive Networks for On-Chip Communication
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Adaptive Networks for On-Chip Communication
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A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications
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Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
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