On the public citation graph

A Flexible High Speed Star Network Based on Peer to Peer Links on FPGA

https://doi.org/10.1109/ispa.2011.40

0 signed · 31 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1093/ietisy/e91-d.9.2312openalex-snapshot

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/ahs.2006.25openalex-snapshot

Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

inferredcites →https://doi.org/10.1109/aina.2010.108openalex-snapshot

Hybrid Communication Reconfigurable Network on Chip for MPSoC

inferredcites →https://doi.org/10.1109/cicc.2005.1626810openalex-snapshot

Dynamically reconfigurable NoC for reconfigurable MPSoC

inferredcites →https://doi.org/10.1109/date.2007.364577openalex-snapshot

An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

inferredcites →https://doi.org/10.1109/fpl.2007.4380710openalex-snapshot

Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System

inferredcites →https://doi.org/10.1109/iccad.2007.4397239openalex-snapshot

Run-time adaptive on-chip communication scheme

inferredcites →https://doi.org/10.1109/ipdps.2007.370388openalex-snapshot

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

inferredcites →https://doi.org/10.1109/ipdps.2009.5161225openalex-snapshot

Evaluation of a multicore reconfigurable architecture with variable core sizes

inferredcites →https://doi.org/10.1109/ipdpsw.2010.5470800openalex-snapshot

High performance reconfigurable multi-processor-based computing on FPGAs

inferredcites →https://doi.org/10.1145/1132952.1132953openalex-snapshot

A survey of research and practices of Network-on-chip

inferredcites →https://doi.org/10.1145/1146909.1146980openalex-snapshot

Overview of the MPSoC design challenge

inferredcites →https://doi.org/10.1145/1736065.1736069openalex-snapshot

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

inferredcites →https://doi.org/10.3233/emc-2005-00034openalex-snapshot

Multi-objective design space exploration of embedded systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.3764openalex-snapshot

An optimal inherently stabilizing routing algorithm for star P2P overlay networks

inferred← citeshttps://doi.org/10.1007/s10766-017-0528-8openalex-snapshot

SparseNN: A Performance-Efficient Accelerator for Large-Scale Sparse Neural Networks

inferred← citeshttps://doi.org/10.1007/s11227-012-0810-xopenalex-snapshot

A star network approach in heterogeneous multiprocessors system on chip

inferred← citeshttps://doi.org/10.1007/s11390-015-1506-5openalex-snapshot

CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data

inferred← citeshttps://doi.org/10.1109/fpl.2012.6339263openalex-snapshot

CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS

inferred← citeshttps://doi.org/10.1109/icws.2016.29openalex-snapshot

FairPlay: Services Migration with Lock-Free Mechanisms for Load Balancing in Cloud Architectures

inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.33openalex-snapshot

Detecting Data Hazards in Multi-Processor System-on-Chips on FPGA

inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.62openalex-snapshot

FPM: A Flexible Programming Model for MPSoC on FPGA

inferred← citeshttps://doi.org/10.1109/ispa/iucc.2017.00098openalex-snapshot

Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network

inferred← citeshttps://doi.org/10.1109/ispa/iucc.2017.00099openalex-snapshot

A High-Performance Accelerator for Large-Scale Convolutional Neural Networks

inferred← citeshttps://doi.org/10.1109/scc.2012.72openalex-snapshot

Regarding Processors and Reconfigurable IP Cores as Services

inferred← citeshttps://doi.org/10.1109/tcbb.2019.2947059openalex-snapshot

GenSeq+: A Scalable High-Performance Accelerator for Genome Sequencing

inferred← citeshttps://doi.org/10.1109/trustcom.2016.0193openalex-snapshot

SCADIS: A Scalable Accelerator for Data-Intensive String Set Matching on FPGAs

inferred← citeshttps://doi.org/10.1109/tsc.2017.2777478openalex-snapshot

SOLAR: Services-oriented Deep Learning Architectures

inferred← citeshttps://doi.org/10.3390/computation7040063openalex-snapshot

Field Programmable Gate Array Applications—A Scientometric Review

inferred← citeshttps://doi.org/10.48550/arxiv.1712.04771openalex-snapshot

Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.