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An Asynchronous Router for Multiple Service Levels Networks on Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1016/j.vlsi.2004.03.006openalex-snapshot
Cost considerations in network on chip
inferredcites →https://doi.org/10.1049/ip-cdt:20030830openalex-snapshot
Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/async.2000.836791openalex-snapshot
Practical design of globally-asynchronous locally-synchronous systems
inferredcites →https://doi.org/10.1109/async.2002.1000296openalex-snapshot
Clock synchronization through handshake signalling
inferredcites →https://doi.org/10.1109/async.2002.1000297openalex-snapshot
Point to point GALS interconnect
inferredcites →https://doi.org/10.1109/async.2003.1199174openalex-snapshot
Self-timed ring for globally-asynchronous locally-synchronous systems
inferredcites →https://doi.org/10.1109/async.2004.1299298openalex-snapshot
Data synchronization issues in GALS SoCs
inferredcites →https://doi.org/10.1109/date.2004.1269067openalex-snapshot
A power and performance model for network-on-chip architectures
inferredcites →https://doi.org/10.1109/date.2004.1269249openalex-snapshot
The design and test of a smartcard chip using a CHAIN self-timed network-on-chip
inferredcites →https://doi.org/10.1109/glsv.1994.289972openalex-snapshot
Basic building blocks for asynchronous packet routers
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/iccd.2000.878271openalex-snapshot
Self calibrating clocks for globally asynchronous locally synchronous systems
inferredcites →https://doi.org/10.1109/icm.2003.238427openalex-snapshot
An asynchronous low latency arbiter for Quality of Service (QoS) applications
inferredcites →https://doi.org/10.1109/isqed.2004.1283698openalex-snapshot
A scalable communication-centric SoC interconnect architecture
inferredcites →https://doi.org/10.1109/mm.2002.1044296openalex-snapshot
Chain: a delay-insensitive chip area interconnect
inferredcites →https://doi.org/10.1109/socc.2004.1362432openalex-snapshot
An asynchronous on-chip network router with quality-of-service (QoS) support
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.1145/988952.988964openalex-snapshot
Quality-of-service and error control techniques for network-on-chip architectures
inferredcites →https://doi.org/10.25405/ncl.34276650openalex-snapshot
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.5555/968880.969260openalex-snapshot
The design and test of a smartcard chip using a CHAIN self-timed network-on-chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Technology‐Aware Communication Architecture Design for Parallel Hardware Platforms
inferred← citeshttps://doi.org/10.1007/978-981-10-8681-6_59openalex-snapshot
Performance Comparison of Asynchronous NoC Router Architectures
inferred← citeshttps://doi.org/10.1007/978-981-13-8942-9_37openalex-snapshot
Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture
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Artificial neural networks based dynamic priority arbitration for asynchronous flow control
inferred← citeshttps://doi.org/10.1007/s10586-017-0979-0openalex-snapshot
GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC
inferred← citeshttps://doi.org/10.1007/s10617-011-9073-7openalex-snapshot
A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications
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Elastic Flow in an Application Specific Network-on-Chip
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.10.003openalex-snapshot
Static timing analysis for modeling QoS in networks-on-chip
inferred← citeshttps://doi.org/10.1016/j.jss.2010.08.024openalex-snapshot
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
inferred← citeshttps://doi.org/10.1016/j.mejo.2011.03.016openalex-snapshot
Low-energy GALS NoC with FIFO—Monitoring dynamic voltage scaling
inferred← citeshttps://doi.org/10.1016/j.vlsi.2008.11.006openalex-snapshot
Two-phase synchronization with sub-cycle latency
inferred← citeshttps://doi.org/10.1016/s1007-0214(09)70027-6openalex-snapshot
Universal GALS platform and evaluation methodology for networks-on-chip
inferred← citeshttps://doi.org/10.1049/iet-cdt.2008.0072openalex-snapshot
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application
inferred← citeshttps://doi.org/10.1049/ip-cdt:20050067openalex-snapshot
Implementation of guaranteed services in the MANGO clockless network-on-chip
inferred← citeshttps://doi.org/10.1109/access.2024.3380477openalex-snapshot
A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/acsd.2012.27openalex-snapshot
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip
inferred← citeshttps://doi.org/10.1109/aina.2008.142openalex-snapshot
Modeling Differentiated Services-Based QoS in Wormhole-Routed NoCs
inferred← citeshttps://doi.org/10.1109/apccas.2014.7032705openalex-snapshot
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips
inferred← citeshttps://doi.org/10.1109/aspdac.2014.6742911openalex-snapshot
A low-latency asynchronous interconnection network with early arbitration resolution
inferred← citeshttps://doi.org/10.1109/async.2006.16openalex-snapshot
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
inferred← citeshttps://doi.org/10.1109/async.2007.15openalex-snapshot
Demystifying Data-Driven and Pausible Clocking Schemes
inferred← citeshttps://doi.org/10.1109/async.2009.13openalex-snapshot
Design and Implementation of a GALS Adapter for ANoC Based Architectures
inferred← citeshttps://doi.org/10.1109/async.2013.25openalex-snapshot
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs
inferred← citeshttps://doi.org/10.1109/async.2019.00013openalex-snapshot
A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols
inferred← citeshttps://doi.org/10.1109/async58294.2023.10239625openalex-snapshot
A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling
inferred← citeshttps://doi.org/10.1109/cads.2010.5623526openalex-snapshot
Dynamic voltage scaling for fully asynchronous NoCs using FIFO threshold levels
inferred← citeshttps://doi.org/10.1109/date.2008.4484872openalex-snapshot
Developing Mesochronous Synchronizers to Enable 3D NoCs
inferred← citeshttps://doi.org/10.1109/date.2009.5090666openalex-snapshot
Aelite: A flit-synchronous Network on Chip with composable and predictable services
inferred← citeshttps://doi.org/10.1109/date.2010.5457239openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferred← citeshttps://doi.org/10.1109/ddecs.2013.6549808openalex-snapshot
A Multi-Credit Flow Control scheme for asynchronous NoCs
inferred← citeshttps://doi.org/10.1109/dtis.2010.5487580openalex-snapshot
Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures
inferred← citeshttps://doi.org/10.1109/icasic.2007.4415860openalex-snapshot
A network-on-Chip system-level simulation environment supporting asynchronous router
inferred← citeshttps://doi.org/10.1109/icm.2006.373261openalex-snapshot
Low-latency Multi-Level Mesh Topology for NoCs
inferred← citeshttps://doi.org/10.1109/icma.2013.6618153openalex-snapshot
Network service connection management mechanism and network service platform
inferred← citeshttps://doi.org/10.1109/icnc.2010.5583826openalex-snapshot
An asynchronous low latency ordered arbiter for network on chips
inferred← citeshttps://doi.org/10.1109/icscs.2008.4746904openalex-snapshot
Design of a NoC-router guaranteeing QoS based on Virtual Channels reservation
inferred← citeshttps://doi.org/10.1109/ictta.2008.4530201openalex-snapshot
Routing Algorithms Study and Comparing in Interconnection Networks
inferred← citeshttps://doi.org/10.1109/idt.2008.4802525openalex-snapshot
A SystemC QoS router design with virtual channels reservation in a wormhole-switched NoC
inferred← citeshttps://doi.org/10.1109/iih-msp.2012.116openalex-snapshot
Server-side Methods for Network Services Management
inferred← citeshttps://doi.org/10.1109/iscas.2015.7169046openalex-snapshot
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)
inferred← citeshttps://doi.org/10.1109/isvlsi.2008.90openalex-snapshot
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
inferred← citeshttps://doi.org/10.1109/isvlsi.2010.44openalex-snapshot
A High Throughput Low Power FIFO Used for GALS NoC Buffers
inferred← citeshttps://doi.org/10.1109/jssc.2016.2611497openalex-snapshot
A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
inferred← citeshttps://doi.org/10.1109/lnet.2020.3010436openalex-snapshot
Toward Fault-Tolerant Deadlock-Free Routing in HyperSurface-Embedded Controller Networks
inferred← citeshttps://doi.org/10.1109/mcsoc.2017.19openalex-snapshot
Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs
inferred← citeshttps://doi.org/10.1109/mdt.2007.164openalex-snapshot
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
inferred← citeshttps://doi.org/10.1109/mwscas57524.2023.10405992openalex-snapshot
Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches
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Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems
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QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
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A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application
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Packet-level static timing analysis for NoCs
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A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
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Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
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Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era
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Asynchronous design of networks-on-chip
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Application specific IP placement for on-chip distributed architectures
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QoS router with both soft and hard guarantee for Network-on-Chip
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A new mechanism to reduce congestion on TDM networks-on-chips
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Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes
inferred← citeshttps://doi.org/10.1109/tc.2013.81openalex-snapshot
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router
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A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
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Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm
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Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
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Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design
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Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
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COMMUNICATION MODELING OF QoS -AWARE WORMHOLE-ROUTED NoCs
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Fault tolerance overhead in network-on-chip flow control schemes
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A survey of research and practices of Network-on-chip
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Developing mesochronous synchronizers to enable 3D NoCs
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Router designs for elastic buffer on-chip networks
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Mesochronous NoC technology for power-efficient GALS MPSoCs
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Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
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Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip
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A Reusable Methodology for High-Performance Interconnects using a Standard-Cell based Asynchronous NoC Router
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Design and integration of high speed relative timed network-on-chip routers
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Design and optimization of asynchronous network-on-chip
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GALS system design: Side channel attack secure cryptographic accelerators
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Runtime Adaptive System-on-Chip Communication Architecture
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Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
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A fully-asynchronous low-power framework for GALS NoC integration
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Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
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A composable and predictable on-chip interconnect
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Conception d'un micro-réseau intégré NOC tolérant les fautes multiples statiques et dynamiques
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Modélisation et gestion du trafic dans le cadre de réseaux sur puce multi-FPGA
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Optimisation de la consommation d’énergie et de la latence dans les réseaux sur puces
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