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GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpca.2010.5416635openalex-snapshot
Graphite: A distributed parallel simulator for multicores
inferredcites →https://doi.org/10.1109/iedm.2005.1609253openalex-snapshot
Scaling, power, and the future of CMOS
inferredcites →https://doi.org/10.1109/ipdps.2004.1303013openalex-snapshot
BigSim: a parallel simulator for performance prediction of extremely large parallel machines
inferredcites →https://doi.org/10.1109/ispa.2009.51openalex-snapshot
Using GPU to Accelerate Cache Simulation
inferredcites →https://doi.org/10.1109/jproc.2006.873612openalex-snapshot
Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs
inferredcites →https://doi.org/10.1109/mdt.2005.136openalex-snapshot
Demystifying 3D ICs: The Pros and Cons of Going Vertical
inferredcites →https://doi.org/10.1109/micro.2007.36openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot
The M5 Simulator: Modeling Networked Systems
inferredcites →https://doi.org/10.1109/mm.2007.66openalex-snapshot
Exploring Large-Scale CMP Architectures Using ManySim
inferredcites →https://doi.org/10.1109/simsym.1991.151499openalex-snapshot
Interactive SPEEDES
inferredcites →https://doi.org/10.1109/vlsid.2007.140openalex-snapshot
Scaling, Power and the Future of CMOS
inferredcites →https://doi.org/10.1109/wsc.1994.717527openalex-snapshot
GTW: a time warp system for shared memory multiprocessors
inferredcites →https://doi.org/10.1109/wsc.1998.745023openalex-snapshot
MPI-SIM: using parallel simulation to evaluate MPI programs
inferredcites →https://doi.org/10.1145/1028176.1006733openalex-snapshot
Evaluation of the Raw Microprocessor
inferredcites →https://doi.org/10.1145/106073.306852openalex-snapshot
Interactive SPEEDES
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1278480.1278667openalex-snapshot
Thousand core chips
inferredcites →https://doi.org/10.1145/1391469.1391679openalex-snapshot
Towards acceleration of fault simulation using graphics processing units
inferredcites →https://doi.org/10.1145/1496909.1496921openalex-snapshot
COTSon
inferredcites →https://doi.org/10.1145/1562764.1562783openalex-snapshot
A view of the parallel computing landscape
inferredcites →https://doi.org/10.1145/158459.158473openalex-snapshot
Breathing Time Warp
inferredcites →https://doi.org/10.1145/1629911.1630056openalex-snapshot
Event-driven gate-level simulation with GP-GPUs
inferredcites →https://doi.org/10.1145/166955.166979openalex-snapshot
The Wisconsin Wind Tunnel: virtual prototyping of parallel computers
inferredcites →https://doi.org/10.1145/182478.182488openalex-snapshot
A distributed memory LAPSE
inferredcites →https://doi.org/10.1145/1837274.1837390openalex-snapshot
RAMP gold
inferredcites →https://doi.org/10.5555/1331699.1331723openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
inferredcites →https://doi.org/10.5555/193201.194885openalex-snapshot
GTW: a time warp system for shared memory multiprocessors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.2940openalex-snapshot
SIMinG‐1k: A thousand‐core simulator running on general‐purpose graphical processing units
inferred← citeshttps://doi.org/10.1007/s10766-018-0566-xopenalex-snapshot
High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858401openalex-snapshot
Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU
inferred← citeshttps://doi.org/10.1109/candar.2017.52openalex-snapshot
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.177openalex-snapshot
VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip
inferred← citeshttps://doi.org/10.1109/mcsoc.2019.00045openalex-snapshot
Designing Application-Specific Heterogeneous Architectures from Performance Models
inferred← citeshttps://doi.org/10.1109/pdp.2016.118openalex-snapshot
Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures
inferred← citeshttps://doi.org/10.1109/tlt.2019.2903714openalex-snapshot
WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming
inferred← citeshttps://doi.org/10.1109/tpds.2014.2319092openalex-snapshot
GPU Acceleration for Simulating Massively Parallel Many-Core Platforms
inferred← citeshttps://doi.org/10.1145/2159430.2159442openalex-snapshot
Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting
inferred← citeshttps://doi.org/10.1145/2870633openalex-snapshot
Performance Evaluation of NoC-Based Multicore Systems
inferred← citeshttps://doi.org/10.1145/2930665openalex-snapshot
VirtualSoC
inferred← citeshttps://doi.org/10.1587/transinf.2018edp7131openalex-snapshot
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept
inferred← citeshttps://doi.org/10.30827/digibug.41909openalex-snapshot
WepSIM: Simulador modular e interactivo de un procesador elemental para facilitar una visión integrada de la microprogramación y la programación en ensamblador
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amr.753-755.2235openalex-snapshot
A GPU-Based Fault Simulator for Small-Delay Faults
inferred← citeshttps://doi.org/10.5821/dissertation-2117-104207openalex-snapshot
A multicore emulator with a profiling infrastructure for transactional memory on FPGA
inferred← citeshttps://doi.org/10.6092/unibo/amsdottorato/6429openalex-snapshot
Parallel Architectures for Many-Core Systems-On-Chip in Deep Sub-Micron Technology
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