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FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/2.982918openalex-snapshot
Asim: a performance model framework
inferredcites →https://doi.org/10.1109/40.768496openalex-snapshot
Environment for PowerPC microarchitecture exploration
inferredcites →https://doi.org/10.1109/hpca.2006.1598110openalex-snapshot
Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors
inferredcites →https://doi.org/10.1109/iccad.2007.4397280openalex-snapshot
The FAST methodology for high-speed SoC/computer simulation
inferredcites →https://doi.org/10.1109/isca.2004.1310787openalex-snapshot
Control flow modeling in statistical simulation for accurate and efficient processor design studies
inferredcites →https://doi.org/10.1109/ispass.2007.363733openalex-snapshot
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
inferredcites →https://doi.org/10.1109/l-ca.2006.14openalex-snapshot
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/mm.2007.39openalex-snapshot
RAMP: Research Accelerator for Multiple Processors
inferredcites →https://doi.org/10.1145/1054907.1054910openalex-snapshot
Mambo
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/244804.244807openalex-snapshot
Using the SimOS machine simulator to study complex computer systems
inferredcites →https://doi.org/10.1145/291069.291063openalex-snapshot
Fast out-of-order processor simulation using memoization
inferredcites →https://doi.org/10.1145/511348.511349openalex-snapshot
Full-system timing-first simulation
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/859626.859629openalex-snapshot
SMARTS
inferredcites →https://doi.org/10.1145/996841.996865openalex-snapshot
The liberty structural specification language

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach
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DSP Instruction Set Simulation
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CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores
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Host-Compiled Simulation
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LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction
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High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors
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ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor
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Sampled Processor Simulation: A Survey
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A Survey of Computer Architecture Simulation Techniques and Tools
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FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture
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A scorchingly fast FPGA-based Precise L1 LRU cache simulator
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GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms
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Exploiting binary translation for fast ASIP design space exploration on FPGAs
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Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation
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Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors
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VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services
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A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory
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The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation
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PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems
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NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping
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Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support
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Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification
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Design space exploration of instruction schedulers for out-of-order soft processors
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A configurable framework for investigating workload execution
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A first-order fine-grained multithreaded throughput model
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Graphite: A distributed parallel simulator for multicores
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Interval simulation: Raising the level of abstraction in architectural simulation
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HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446098openalex-snapshot
LiveSim: Going live with microarchitecture simulation
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ALWP: A Workload Partition Method for the Efficient Parallel Simulation of Manycores
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PartitionSim: A Parallel Simulator for Many-cores
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Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
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FastLanes: An FPGA accelerated GPU microarchitecture simulator
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GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
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Boosting Domain-Specific Debug Through Inter-frame Compression
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TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
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Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
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DDGSim: GPU based simulator for large multicore with bufferless NoC
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Parallelizing computer system simulators
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HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices
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Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL
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FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
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The Dataflow Abstract Machine Simulator Framework
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Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs
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QUICK: A flexible full-system functional model
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An FPGA-based multi-core platform for testing and analysis of architectural techniques
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Fast and cycle-accurate modeling of a multicore processor
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FPGA modeling of diverse superscalar processors
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PriME: A parallel and distributed simulator for thousand-core chips
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Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation
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A general technique for deterministic model-cycle-level debugging
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RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
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Early Models for System-Level Power Estimation
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Speed up an x86 SAME simulator using synthesizable SystemC timing models
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Sampling-based approaches to accelerate network-on-chip simulation
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P-GAS: Parallelizing a Cycle-Accurate Event-Driven Many-Core Processor Simulator Using Parallel Discrete Event Simulation
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Host-compiled simulation of multi-core platforms
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Accelerating manycore simulation by efficient NoC interconnection partition on FPGA simulation platform
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Evaluation methods of computer memory system
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Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper
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Less reused filter
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High performance cache replacement using re-reference interval prediction (RRIP)
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High performance cache replacement using re-reference interval prediction (RRIP)
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Prototyping hardware support for irregular applications
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ZSim
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ZSim
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Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
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SynFull
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Accurate phase-level cross-platform power and performance estimation
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Strober
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On making xen detect hypercalls and memory accesses for simulating virtualization-enabled processors
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PAQSIM
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FirePerf
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gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator
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SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud
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Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion
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Enabling Fast ASIP Design Space Exploration: An FPGA‐Based Runtime Reconfigurable Prototyper
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An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters
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Computer Architecture Performance Evaluation Methods
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Multi-Core Cache Hierarchies
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A highly efficient full-system virtual prototype based on virtualization-assisted approach
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Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC
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Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization
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Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation
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FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits
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EPSim-C: A Parallel Epoch-Based Cycle-Accurate Microarchitecture Simulator Using Cloud Computing
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Simulation methodologies for future large-scale parallel systems
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Multicore architecture prototyping on reconfigurable devices
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Stratégies de parallélisation espace-temps pour la simulation numérique des écoulements turbulents
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Étude d'architectures dédiées aux systèmes embarqués intelligents et efficaces en énergie
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Behavioral Application-dependent superscolor core modeling
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Accurate Simulation of Data Movement in Modern Mobile Multicore Systems
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Systèmes intégrés adaptatifs ultra basse consommation pour l’Internet des Objets
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