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A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/5.469298openalex-snapshot
Service disciplines for guaranteed performance service in packet-switching networks
inferredcites →https://doi.org/10.1109/90.986511openalex-snapshot
A framework for guaranteeing statistical QoS
inferredcites →https://doi.org/10.1109/cicc.1998.694912openalex-snapshot
Integration architecture for system-on-a-chip design
inferredcites →https://doi.org/10.1109/dac.2001.935469openalex-snapshot
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
inferredcites →https://doi.org/10.1109/date.2002.998309openalex-snapshot
Networks on silicon: combining best-effort and guaranteed services
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/dsd.2002.1115369openalex-snapshot
Networks on silicon: blessing or nightmare?
inferredcites →https://doi.org/10.1109/infcom.1996.497884openalex-snapshot
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot
Virtual-channel flow control
inferredcites →https://doi.org/10.1145/173942.173943openalex-snapshot
Open issues and challenges in providing quality of service guarantees in high-speed networks
inferredcites →https://doi.org/10.1145/378239.379046openalex-snapshot
Micronetwork-based integration for SOCs
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Platforms and Architectures for Distributed Smart Cameras
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Embedded Computer Vision
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Embedded Computer Vision
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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications
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Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC
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Network and Transport Layers in Networks on Chip
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Design Methodologies and CAD Tool Flows for NoCs
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CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
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Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
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An analytical model of broadcast in QoS-aware wormhole-routed NoCs
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Runtime connection-oriented guaranteed-bandwidth network-on-chip with extra multicast communication service
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Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis
inferred← citeshttps://doi.org/10.1049/iet-cdt:20060152openalex-snapshot
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism[Note 1]
inferred← citeshttps://doi.org/10.1093/ietisy/e90-d.3.676openalex-snapshot
Latency-Aware Bus Arbitration for Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/aina.2008.142openalex-snapshot
Modeling Differentiated Services-Based QoS in Wormhole-Routed NoCs
inferred← citeshttps://doi.org/10.1109/aspdac.2007.357979openalex-snapshot
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657088openalex-snapshot
Resource allocation algorithms for guaranteed service in application-specific NoCs
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00029openalex-snapshot
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
inferred← citeshttps://doi.org/10.1109/isqed.2006.41openalex-snapshot
Core Network Interface Architecture and Latency Constrained On-Chip Communication
inferred← citeshttps://doi.org/10.1109/mdt.2005.108openalex-snapshot
Design, Synthesis, and Test of Networks on Chips
inferred← citeshttps://doi.org/10.1109/micro.2010.18openalex-snapshot
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
inferred← citeshttps://doi.org/10.1109/micro.2010.21openalex-snapshot
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
inferred← citeshttps://doi.org/10.1109/norchp.2009.5397831openalex-snapshot
QoS router with both soft and hard guarantee for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/sta50679.2020.9329296openalex-snapshot
A Secure Network Interface for on-Chip Systems
inferred← citeshttps://doi.org/10.1109/tc.2012.241openalex-snapshot
Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement
inferred← citeshttps://doi.org/10.1109/tcad.2015.2488490openalex-snapshot
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels
inferred← citeshttps://doi.org/10.1109/tce.2018.2843287openalex-snapshot
Dynamic Transaction Management for System Level Quality-of-Service in Mobile APs
inferred← citeshttps://doi.org/10.1142/s0219265908002357openalex-snapshot
COMMUNICATION MODELING OF QoS -AWARE WORMHOLE-ROUTED NoCs
inferred← citeshttps://doi.org/10.1145/1132952.1132953openalex-snapshot
A survey of research and practices of Network-on-chip
inferred← citeshttps://doi.org/10.1145/1278480.1278510openalex-snapshot
Introducing the SuperGT network-on-chip
inferred← citeshttps://doi.org/10.1145/1394608.1382130openalex-snapshot
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
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The aethereal network on chip after ten years
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Dynamic QoS management for chip multiprocessors
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Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
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Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems
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