On the public citation graph
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
0 signed · 69 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1109/date.2005.33openalex-snapshot
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/iccd.2006.4380859openalex-snapshot
Implementation and Evaluation of On-Chip Network Architectures
inferredcites →https://doi.org/10.1109/iccd.2007.4601881openalex-snapshot
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
inferredcites →https://doi.org/10.1109/isca.2008.31openalex-snapshot
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/micro.2004.4openalex-snapshot
Adaptive History-Based Memory Schedulers
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1109/tpds.2002.1158264openalex-snapshot
Mediaworm: a qos capable router architecture for clusters
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1362622.1362630openalex-snapshot
Age-based packet arbitration in large-radix k -ary n -cubes
inferredcites →https://doi.org/10.1145/1555754.1555810openalex-snapshot
Achieving predictable performance through better memory controller placement in many-core CMPs
inferredcites →https://doi.org/10.1145/232973.232996openalex-snapshot
Rotating combined queueing (RCQ)
inferredcites →https://doi.org/10.1145/233008.233030openalex-snapshot
Design and analysis of frame-based fair queueing
inferredcites →https://doi.org/10.1145/75246.75248openalex-snapshot
Analysis and simulation of a fair queueing algorithm
inferredcites →https://doi.org/10.1145/75247.75248openalex-snapshot
Analysis and simulation of a fair queueing algorithm
inferredcites →https://doi.org/10.1145/99508.99525openalex-snapshot
Virtual clock: a new traffic control algorithm for packet switching networks
inferredcites →https://doi.org/10.1145/99517.99525openalex-snapshot
Virtual clock: a new traffic control algorithm for packet switching networks
inferredcites →https://doi.org/10.5555/1267638.1267639openalex-snapshot
Lottery scheduling: flexible proportional-share resource management
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-35473-1_76openalex-snapshot
Asynchronous Ring Network Mechanism with a Fair Arbitration Strategy for Network on Chip
inferred← citeshttps://doi.org/10.1007/s11227-016-1758-zopenalex-snapshot
Network unfairness in dragonfly topologies
inferred← citeshttps://doi.org/10.1016/j.jpdc.2012.01.013openalex-snapshot
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
inferred← citeshttps://doi.org/10.1049/iet-cdt.2015.0049openalex-snapshot
Adaptively weighted round‐robin arbitration for equality of service in a many‐core network‐on‐chip
inferred← citeshttps://doi.org/10.1109/aspdac.2015.7058981openalex-snapshot
Adaptive remaining hop count flow control: Consider the interaction between packets
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586301openalex-snapshot
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC
inferred← citeshttps://doi.org/10.1109/edcav.2015.7060540openalex-snapshot
Problems encountered in various arbitration techniques used in NOC router: A survey
inferred← citeshttps://doi.org/10.1109/euc.2014.17openalex-snapshot
Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00058openalex-snapshot
Experiences with ML-Driven Design: A NoC Case Study
inferred← citeshttps://doi.org/10.1109/icct62929.2024.10874929openalex-snapshot
Inverse Weight Based Arbitration Algorithm for On-Chip Networks
inferred← citeshttps://doi.org/10.1109/icecds.2017.8390010openalex-snapshot
A survey on QOS routing techniques used in network on chip
inferred← citeshttps://doi.org/10.1109/ipdps.2014.94openalex-snapshot
Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.114openalex-snapshot
Achieving Global Fairness for On-Chip Network Using Group Allocation
inferred← citeshttps://doi.org/10.1109/isca.2014.6853238openalex-snapshot
Unifying on-chip and inter-node switching within the Anton 2 network
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferred← citeshttps://doi.org/10.1109/isscc.2012.6177098openalex-snapshot
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS
inferred← citeshttps://doi.org/10.1109/lca.2015.2428699openalex-snapshot
Towards High-Performance Bufferless NoCs with SCEPTER
inferred← citeshttps://doi.org/10.1109/micro.2014.19openalex-snapshot
Dodec: Random-Link, Low-Radix On-Chip Networks
inferred← citeshttps://doi.org/10.1109/micro.2014.45openalex-snapshot
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration
inferred← citeshttps://doi.org/10.1109/micro.2014.61openalex-snapshot
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00070openalex-snapshot
Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture
inferred← citeshttps://doi.org/10.1109/nesea.2011.6144932openalex-snapshot
Group allocation: A novel fairness mechanism for on-chip network
inferred← citeshttps://doi.org/10.1109/pact.2019.00016openalex-snapshot
Enforcing Last-Level Cache Partitioning through Memory Virtual Channels
inferred← citeshttps://doi.org/10.1109/socc.2011.6085085openalex-snapshot
Fair rate packet arbitration in Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2012.241openalex-snapshot
Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement
inferred← citeshttps://doi.org/10.1109/tc.2016.2519884openalex-snapshot
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tencon.2017.8228281openalex-snapshot
Buffer aware arbiter design to achieve improved QoS for NoC
inferred← citeshttps://doi.org/10.1109/tpds.2017.2713778openalex-snapshot
A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches
inferred← citeshttps://doi.org/10.1145/2228360.2228432openalex-snapshot
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service
inferred← citeshttps://doi.org/10.1145/2401716.2401728openalex-snapshot
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips
inferred← citeshttps://doi.org/10.1145/2509420.2512429openalex-snapshot
Designing on-chip networks for throughput accelerators
inferred← citeshttps://doi.org/10.1145/2678373.2665677openalex-snapshot
Unifying on-chip and inter-node switching within the Anton 2 network
inferred← citeshttps://doi.org/10.1145/2897394openalex-snapshot
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory
inferred← citeshttps://doi.org/10.1145/3037697.3037753openalex-snapshot
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers
inferred← citeshttps://doi.org/10.1145/3093315.3037753openalex-snapshot
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers
inferred← citeshttps://doi.org/10.1145/3093336.3037753openalex-snapshot
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers
inferred← citeshttps://doi.org/10.1145/3093337.3037753openalex-snapshot
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers
inferred← citeshttps://doi.org/10.1145/3290688.3290706openalex-snapshot
Impact of Network Fairness on the Performance of Parallel Systems
inferred← citeshttps://doi.org/10.1145/3470496.3527405openalex-snapshot
A software-defined tensor streaming multiprocessor for large-scale machine learning
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.4995/thesis/10251/112423openalex-snapshot
Adaptive Prefetching and Cache Partitioning for Multicore Processors
inferred← citeshttps://doi.org/10.7251/ijeec2002135sopenalex-snapshot
Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.