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An Application-Specific Design Methodology for STbus Crossbar Generation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Optimization of Reliability and Power Consumption in Systems on a Chip
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Approximation Algorithms
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QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
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Viper: A multiprocessor SOC for advanced set-top box and digital TV systems
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Constraint-driven bus matrix synthesis for MPSoC
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Constraint-driven communication synthesis
inferredcites →https://doi.org/10.1109/dac.2002.1012730openalex-snapshot
Component-based design approach for multicore SoCs
inferredcites →https://doi.org/10.1109/date.2000.840047openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/date.2003.1253687openalex-snapshot
Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures
inferredcites →https://doi.org/10.1109/date.2004.1268966openalex-snapshot
Analyzing on-chip communication in a MPSoC environment
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2006.244007openalex-snapshot
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
inferredcites →https://doi.org/10.1109/hpca.2003.1183554openalex-snapshot
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
inferredcites →https://doi.org/10.1109/iccd.2003.1240887openalex-snapshot
Efficient synthesis of networks on chip
inferredcites →https://doi.org/10.1109/isss.1995.520627openalex-snapshot
Synthesis of system-level communication by an allocation-based approach
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1109/tcad.2004.826585openalex-snapshot
Design of High-Performance System-On-Chips Using Communication Architecture Tuners
inferredcites →https://doi.org/10.1109/tcad.2004.828127openalex-snapshot
Design Space Exploration for Optimizing On-Chip Communication Architectures
inferredcites →https://doi.org/10.1109/tcad.2004.835119openalex-snapshot
Automated Bus Generation for Multiprocessor SoC Design
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1109/tvlsi.2003.817546openalex-snapshot
Fixed-outline floorplanning: enabling hierarchical design
inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot
A unified approach to constrained mapping and routing on network-on-chip architectures
inferredcites →https://doi.org/10.1145/1118299.1118344openalex-snapshot
Mapping and configuration methods for multi-use-case networks on chips
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/224486.224534openalex-snapshot
Synthesis of system-level communication by an allocation-based approach
inferredcites →https://doi.org/10.1145/298865.298866openalex-snapshot
Bus-based communication synthesis on system level
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
inferredcites →https://doi.org/10.1145/378239.379046openalex-snapshot
Micronetwork-based integration for SOCs
inferredcites →https://doi.org/10.1145/513918.514114openalex-snapshot
Constraint-driven communication synthesis
inferredcites →https://doi.org/10.1145/513918.514115openalex-snapshot
Component-based design approach for multicore SoCs
inferredcites →https://doi.org/10.1145/966747.966758openalex-snapshot
Topology optimization for application-specific networks-on-chip
inferredcites →https://doi.org/10.1145/996566.996753openalex-snapshot
The future of multiprocessor systems-on-chips
inferredcites →https://doi.org/10.5555/1129601.1129635openalex-snapshot
An automated technique for topology and route generation of application specific on-chip interconnection networks
inferredcites →https://doi.org/10.5555/224841.225053openalex-snapshot
Communication synthesis for distributed embedded systems
inferredcites →https://doi.org/10.5555/789083.1022740openalex-snapshot
Automated Bus Generation for Multiprocessor SoC Design
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
inferredcites →https://doi.org/10.5555/789083.1022804openalex-snapshot
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks
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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications
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Design Trade-offs in Customized On-chip Crossbar Schedulers
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Basic Concepts of Bus-Based Communication Architectures
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Synthesis of On-Chip Communication Architectures
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Network Architecture
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Elastic Flow in an Application Specific Network-on-Chip
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Design automation for application-specific on-chip interconnects: A survey
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Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis
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Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning
inferred← citeshttps://doi.org/10.1109/acdsa65407.2025.11165816openalex-snapshot
Fault-Tolerant Adaptive Routing in NoCs: Machine Learning Approaches for Resilient On-Chip Networks
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Using TLM for Exploring Bus-based SoC Communication Architectures
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Mapping and Topology Customization Approaches for Application-Specific STNoC Designs
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Constraint-driven bus matrix synthesis for MPSoC
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Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
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Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
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Online Test Macro Scheduling and Assignment in MPSoC Design
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Application Specific NoC Design
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COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC
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Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms
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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
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Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
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Application-Specific Topology Design Customization for STNoC
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Application-Specific Topology Design Customization for STNoC
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Automatic Topology Optimization for FPGA Interconnect Synthesis
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Designing Application-Specific Networks on Chips with Floorplan Information
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Crossbar Bus Synthesis on Transaction Level Using Genetic Algorithm
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Crossbar Bus Synthesis on Transaction Level Using Genetic Algorithm
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A high-throughput and size-efficient NoC buffer design method
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Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration
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Automatic crossbarbus-based system level communication synthesis
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A Trojan-resistant system-on-chip bus architecture
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Implementation of a Configurable Crossbar Switch for Prototyping of Single-Chip Multiprocessors
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Expression of Concern: Implementing DSP Algorithms with On-Chip Networks
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Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network
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Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis
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A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC
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An Application-Specific Design Methodology for On-Chip Crossbar Generation
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BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC
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Topology Synthesis of Cascaded Crossbar Switches
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The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip
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