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Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards
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Outgoing claims: the papers this work cites, builds on, or argues with.
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TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
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Trace-Driven Memory Simulation: A Survey
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The Datacenter as a Computer
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Computer Architecture Performance Evaluation Methods
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Global Extensible Open Power Manager: A Vehicle for HPC Community Collaboration on Co-Designed Energy Management Solutions
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A Modern Primer on Processing in Memory
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NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture
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Performance issues in dataflow machines
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A Survey on quantum computing technology
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Limits on fundamental limits to computation
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Training and operation of an integrated neuromorphic network based on metal-oxide memristors
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Equivalent-accuracy accelerated neural-network training using analogue memory
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A method to estimate the energy consumption of deep neural networks
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The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture
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The Power of ARM64 in Public Clouds
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AMD SOC power management: Improving performance/watt using run-time feedback
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NeuFlow: A runtime reconfigurable dataflow processor for vision
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RTL C-based methodology for designing and verifying a multi-threaded processor
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An Efficient Sequential SAT Solver With Improved Search Strategies
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Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors
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A Study of Performance and Power Consumption Differences Among Different ISAs
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AMD Next Generation 7NM Ryzen™ 4000 APU "Renoir"
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Hybrid memory cube (HMC)
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Amdahl’s Law in the multicore era
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The Accelerator Wall: Limits of Chip Specialization
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Enhancing Server Efficiency in the Face of Killer Microseconds
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Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices
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Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance
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NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations
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MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology
inferredcites →https://doi.org/10.1109/iiswc.2017.8167757openalex-snapshot
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Understanding power-performance relationship of energy-efficient modern DRAM devices
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Memory scaling: A systems architecture perspective
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An Energy Efficiency Feature Survey of the Intel Haswell Processor
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Wattch: a framework for architectural-level power analysis and optimizations
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RAIDR: Retention-aware intelligent DRAM refresh
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Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
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Architecture implications of pads as a scarce resource
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ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
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PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
inferredcites →https://doi.org/10.1109/isca.2016.32openalex-snapshot
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
inferredcites →https://doi.org/10.1109/isca.2016.40openalex-snapshot
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/isca.2016.41openalex-snapshot
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory
inferredcites →https://doi.org/10.1109/isca.2018.00014openalex-snapshot
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
inferredcites →https://doi.org/10.1109/isca45697.2020.00029openalex-snapshot
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
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PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isqed.2009.4810377openalex-snapshot
Impact of SoC power management techniques on verification and testing
inferredcites →https://doi.org/10.1109/isqed.2019.8697354openalex-snapshot
Towards Energy Efficient non-von Neumann Architectures for Deep Learning
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A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors
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No exponential is forever: but "Forever" can be delayed! [semiconductor industry]
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NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories
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Cramming More Components Onto Integrated Circuits
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Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions
inferredcites →https://doi.org/10.1109/jproc.2021.3067593openalex-snapshot
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook
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Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/jssc.2014.2360379openalex-snapshot
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
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Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management
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Ramulator: A Fast and Extensible DRAM Simulator
inferredcites →https://doi.org/10.1109/lca.2020.2973991openalex-snapshot
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator
inferredcites →https://doi.org/10.1109/mc.2007.443openalex-snapshot
The Case for Energy-Proportional Computing
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Amdahl's Law in the Multicore Era
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Energy-Efficient Abundant-Data Computing: The N3XT 1,000x
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Bridging the Processor-Memory Performance Gapwith 3D IC Technology
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A GALS Infrastructure for a Massively Parallel Multiprocessor
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Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
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Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions
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CoScale: Coordinating CPU and Memory System DVFS in Server Systems
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Improving energy efficiency of DRAM by exploiting half page row access
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Near-Data Processing: Insights from a MICRO-46 Workshop
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Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake
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Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
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Compute Solution for Tesla's Full Self-Driving Computer
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AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers
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A study of application performance with non-volatile main memory
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Dynamic power management with power network-on-chip
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SpinNNaker: The world's biggest NoC
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Advanced SoC virtual prototyping for system-level power planning and validation
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Modeling energy-performance tradeoffs in ARM big.LITTLE architectures
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Memory-Aware Dynamic Voltage and Frequency Prediction for Portable Devices
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Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors
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Trace Scheduling: A Technique for Global Microcode Compaction
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
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Multi-threshold CMOS design for low power digital circuits
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Thermal Prediction for Efficient Energy Management of Clouds Using Machine Learning
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Power estimation techniques for FPGAs
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Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
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Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
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Microarchitectural techniques for power gating of execution units
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Recent extensions to the SimpleScalar tool suite
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Limits of instruction-level parallelism
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Limits of instruction-level parallelism
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Limits of instruction-level parallelism
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Power reduction techniques for microprocessor systems
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Validity of the single processor approach to achieving large scale computing capabilities
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SOI, interconnect, package, and mainboard thermal characterization
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Functional verification of power gate design in SystemC RTL
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Phase change memory architecture and the quest for scalability
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Understanding sources of inefficiency in general-purpose chips
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Understanding sources of inefficiency in general-purpose chips
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Memory power management via dynamic voltage/frequency scaling
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Near-threshold voltage (NTV) design
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Power Limitations and Dark Silicon Challenge the Future of Multicore
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A Survey of Methods for Analyzing and Improving GPU Energy Efficiency
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Complexity-effective superscalar processors
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Exploring the potential of heterogeneous von neumann/dataflow execution models
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A scalable processing-in-memory accelerator for parallel graph processing
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Energy Efficient Job Scheduling with DVFS for CPU-GPU Heterogeneous Systems
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Understanding Reduced-Voltage Operation in Modern DRAM Devices
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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A Survey of Chip-level Thermal Simulators
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Energy-driven integrated hardware-software optimizations using SimplePower
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Energy-driven integrated hardware-software optimizations using SimplePower
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AccelWattch: A Power Modeling Framework for Modern GPUs
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Complexity-effective superscalar processors
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Temperature-aware microarchitecture
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Dataflow Architectures
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Three-dimensional silicon integration
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An Efficient Algorithm for Exploiting Multiple Arithmetic Units
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Irreversibility and heat generation in the computing process
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Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
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New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
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Phase-change random access memory: A scalable technology
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Recent Subthreshold Design Techniques
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Power Management Methods: From Specification and Modeling, to Techniques and Verification
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Feynman Lectures on Computation
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A Comparison of x86 Computer Architecture Simulators
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Power Analyzer for Pocket Computing (PAPC)
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Computer Architecture Techniques for Power-Efficiency
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The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
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Computer Architecture Performance Evaluation Methods
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Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators
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Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain
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A Taxonomy and Future Directions for Sustainable Cloud Computing: 360 Degree View
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The Architectural Implications of Microservices in the Cloud
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Memristors -- from In-memory computing, Deep Learning Acceleration, Spiking Neural Networks, to the Future of Neuromorphic and Bio-inspired Computing
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48 Years of Microprocessor Trend Data
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PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
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Tutorial: Design and Optimization of Power Delivery Networks
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Cramming More Components onto Integrated Circuits (1965)
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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inferred← citeshttps://doi.org/10.1088/1742-6596/2628/1/012029openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/access.2025.3547808openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/fie63693.2025.11328713openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/histelcon64051.2025.11286127openalex-snapshot
Energy Consumption in Computing over the Decades: Trends, Efficiency, and Measurement Challenges
inferred← citeshttps://doi.org/10.1109/icacs64902.2025.10937815openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icmi68585.2026.11539767openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icsedis68157.2026.11518437openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/jsen.2024.3461833openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/pacet68758.2026.11498237openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2023.3307796openalex-snapshot
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TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link
inferred← citeshttps://doi.org/10.1109/tcad.2025.3571314openalex-snapshot
LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer
inferred← citeshttps://doi.org/10.1109/tqcebt59414.2024.10545213openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3415486openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/upcon56432.2022.9986479openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/wsc68292.2025.11338900openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3548606.3560682openalex-snapshot
Frequency Throttling Side-Channel Attack
inferred← citeshttps://doi.org/10.1145/3579992openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3676536.3676778openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3725887openalex-snapshot
DeepPM: Predicting Performance and Energy Consumption of Program Binaries Using Transformers
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Carbon-Efficient Software Design and Development: A Systematic Literature Review
inferred← citeshttps://doi.org/10.1145/3732937openalex-snapshot
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inferred← citeshttps://doi.org/10.1177/10692509261477252openalex-snapshot
Deterministic population initialization for multi-objective mapping of multiple applications in network-on-chip-based many-core systems
inferred← citeshttps://doi.org/10.1364/ome.609065openalex-snapshot
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inferred← citeshttps://doi.org/10.2139/ssrn.5180499openalex-snapshot
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inferred← citeshttps://doi.org/10.2139/ssrn.7443052openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/bdcc7020108openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/electronics13101805openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/electronics14122328openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/electronics14244787openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/info17060596openalex-snapshot
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inferred← citeshttps://doi.org/10.3390/math13172820openalex-snapshot
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inferred← citeshttps://doi.org/10.3929/ethz-b-000643341openalex-snapshot
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inferred← citeshttps://doi.org/10.61453/jods.v20260209openalex-snapshot
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inferred← citeshttps://doi.org/10.63775/hk5d1t79openalex-snapshot
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inferred← citeshttps://doi.org/10.7498/aps.72.20231546openalex-snapshot
Phononic thermal conduction and thermal regulation in low-dimensional micro-nano scale systems: Nonequilibrium statistical physics problems from chip heat dissipation
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