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Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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How to Break MD5 and Other Hash Functions
inferredcites →https://doi.org/10.1007/11545262_32openalex-snapshot
A Very Compact S-Box for AES
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A Comparative Cost/Security Analysis of Fault Attack Countermeasures
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A Compact Rijndael Hardware Architecture with S-Box Optimization
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An ASIC Implementation of the AES SBoxes
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High-Performance Concurrent Error Detection Scheme for AES Hardware
inferredcites →https://doi.org/10.1007/978-3-540-85174-5_11openalex-snapshot
Preimages for Reduced SHA-0 and SHA-1
inferredcites →https://doi.org/10.1007/978-3-642-15031-9_10openalex-snapshot
Side-Channel Analysis of Six SHA-3 Candidates
inferredcites →https://doi.org/10.1007/978-3-642-15031-9_18openalex-snapshot
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
inferredcites →https://doi.org/10.1080/0161-110291890876openalex-snapshot
THE ADVANCED ENCRYPTION STANDARD
inferredcites →https://doi.org/10.1109/dft.2006.50openalex-snapshot
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
inferredcites →https://doi.org/10.1109/dftvs.2001.966796openalex-snapshot
Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture
inferredcites →https://doi.org/10.1109/dftvs.2002.1173501openalex-snapshot
A parity code based fault detection for an implementation of the Advanced Encryption Standard
inferredcites →https://doi.org/10.1109/dftvs.2004.1347833openalex-snapshot
An efficient hardware-based fault diagnosis scheme for AES: performances and cost
inferredcites →https://doi.org/10.1109/tc.2003.1190590openalex-snapshot
Error analysis and detection procedures for a hardware implementation of the advanced encryption standard
inferredcites →https://doi.org/10.1109/tc.2006.143openalex-snapshot
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
inferredcites →https://doi.org/10.1109/tc.2007.1015openalex-snapshot
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers
inferredcites →https://doi.org/10.1109/tc.2008.149openalex-snapshot
Double-Data-Rate Computation as a Countermeasure against Fault Analysis
inferredcites →https://doi.org/10.1109/tc.2010.33openalex-snapshot
Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard
inferredcites →https://doi.org/10.1109/tvlsi.2004.832943openalex-snapshot
High-speed VLSI architectures for the AES algorithm
inferredcites →https://doi.org/10.1109/tvlsi.2009.2031651openalex-snapshot
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields
inferredcites →https://doi.org/10.1587/transfun.e94.a.1318openalex-snapshot
Mixed Bases for Efficient Inversion in F((22)2)2 and Conversion Matrices of SubBytes of AES

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Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Reliable hash trees for post-quantum stateless cryptographic hash-based signatures
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Correction of MEU Errors in AES Using Multi Bit Errors Correction Technique
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Efficient error detection architectures for CORDIC through recomputing with encoded operands
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Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes
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