On the public citation graph
From Embedded Test to Embedded Diagnosis
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s10677-004-4249-xopenalex-snapshot
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*
inferredcites →https://doi.org/10.1023/a:1024636424035openalex-snapshot
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
inferredcites →https://doi.org/10.1049/ip-cdt:20030834openalex-snapshot
Delay defect diagnosis based upon a statistical timing model – the first step
inferredcites →https://doi.org/10.1109/12.262119openalex-snapshot
Diagnosis by signature analysis of test responses
inferredcites →https://doi.org/10.1109/12.364534openalex-snapshot
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
inferredcites →https://doi.org/10.1109/12.559802openalex-snapshot
On dictionary-based fault location in digital logic circuits
inferredcites →https://doi.org/10.1109/12.780879openalex-snapshot
Diagnosis of scan cells in BIST environment
inferredcites →https://doi.org/10.1109/12.862216openalex-snapshot
Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines
inferredcites →https://doi.org/10.1109/43.748164openalex-snapshot
Creating small fault dictionaries [logic circuit fault diagnosis]
inferredcites →https://doi.org/10.1109/43.790625openalex-snapshot
Fault emulation: A new methodology for fault grading
inferredcites →https://doi.org/10.1109/54.980052openalex-snapshot
Cost-effective deterministic partitioning for rapid diagnosis in scan-based BIST
inferredcites →https://doi.org/10.1109/dac.2002.1012630openalex-snapshot
Effective diagnostics through interval unloads in a BIST environment
inferredcites →https://doi.org/10.1109/date.2001.915008openalex-snapshot
Diagnosis for scan-based BIST: reaching deep into the signatures
inferredcites →https://doi.org/10.1109/date.2002.998301openalex-snapshot
Gate level fault diagnosis in scan-based BIST
inferredcites →https://doi.org/10.1109/date.2003.1253627openalex-snapshot
Non-enumerative path delay fault diagnosis [logic testing]
inferredcites →https://doi.org/10.1109/date.2004.1268981openalex-snapshot
Impact of test point insertion on silicon area and timing during layout
inferredcites →https://doi.org/10.1109/date.2004.1269035openalex-snapshot
Intermittent scan chain fault diagnosis based on signal probability analysis
inferredcites →https://doi.org/10.1109/date.2004.1269075openalex-snapshot
Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes
inferredcites →https://doi.org/10.1109/ftcsh.1995.532648openalex-snapshot
AN ENHANCEMENT TO LSSD AND SOME APPLICATIONS OF LSSD IN RELIABILITY, AVAILABILITY, AND SERVICEABILIT
inferredcites →https://doi.org/10.1109/iccad.1995.480010openalex-snapshot
On adaptive diagnostic test generation
inferredcites →https://doi.org/10.1109/iccad.1995.480011openalex-snapshot
Diagnosis of realistic bridging faults with single stuck-at information
inferredcites →https://doi.org/10.1109/iccad.1997.643595openalex-snapshot
A deductive technique for diagnosis of bridging faults
inferredcites →https://doi.org/10.1109/icvd.2001.902690openalex-snapshot
Efficient signature-based fault diagnosis using variable size windows
inferredcites →https://doi.org/10.1109/mdt.2002.1033794openalex-snapshot
Extending OPMISR beyond 10× scan test efficiency
inferredcites →https://doi.org/10.1109/tc.2004.4openalex-snapshot
Compact dictionaries for fault diagnosis in scan-BIST
inferredcites →https://doi.org/10.1109/tcad.2003.810739openalex-snapshot
Failing vector identification based on overlapping intervals of test vectors in a scan-bist environment
inferredcites →https://doi.org/10.1109/tcad.2004.823341openalex-snapshot
X-Compact: An Efficient Response Compaction Technique
inferredcites →https://doi.org/10.1109/test.1991.519700openalex-snapshot
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
inferredcites →https://doi.org/10.1109/test.1992.527892openalex-snapshot
Skewed-Load Transition Test: Part I, Calculus
inferredcites →https://doi.org/10.1109/test.1995.529878openalex-snapshot
Timing-driven test point insertion for full-scan and partial-scan BIST
inferredcites →https://doi.org/10.1109/test.1996.556959openalex-snapshot
Altering a pseudo-random bit sequence for scan-based BIST
inferredcites →https://doi.org/10.1109/test.1996.557122openalex-snapshot
Constructive multi-phase test point insertion for scan-based BIST
inferredcites →https://doi.org/10.1109/test.1997.639704openalex-snapshot
Fault diagnosis in scan-based BIST
inferredcites →https://doi.org/10.1109/test.2000.894213openalex-snapshot
POIROT: a logic fault diagnosis tool and its applications
inferredcites →https://doi.org/10.1109/test.2002.1041768openalex-snapshot
An effective diagnosis method to support yield improvement
inferredcites →https://doi.org/10.1109/test.2002.1041773openalex-snapshot
Embedded deterministic test for low cost manufacturing test
inferredcites →https://doi.org/10.1109/test.2003.1270856openalex-snapshot
Diagnosis-based post-silicon timing validation using statistical tools and methodologies
inferredcites →https://doi.org/10.1109/test.2003.1270904openalex-snapshot
Convolutional compaction of test responses
inferredcites →https://doi.org/10.1109/test.2003.1271093openalex-snapshot
Simulating resistive bridging and stuck-at faults
inferredcites →https://doi.org/10.1109/test.2003.1271094openalex-snapshot
On-chip compression of output responses with unknown values using lfsr reseeding
inferredcites →https://doi.org/10.1109/test.2004.1386936openalex-snapshot
Efficient pattern mapping for deterministic logic BIST
inferredcites →https://doi.org/10.1109/test.2004.1386980openalex-snapshot
X-masking during logic BIST and its impact on defect coverage
inferredcites →https://doi.org/10.1109/tvlsi.2005.863742openalex-snapshot
X-masking during logic BIST and its impact on defect coverage
inferredcites →https://doi.org/10.1109/vtest.1995.512635openalex-snapshot
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
inferredcites →https://doi.org/10.1109/vtest.1999.766661openalex-snapshot
Adaptive techniques for improving delay fault diagnosis
inferredcites →https://doi.org/10.1109/vtest.2000.843860openalex-snapshot
A technique for logic fault diagnosis of interconnect open defects
inferredcites →https://doi.org/10.1109/vtest.2003.1197640openalex-snapshot
Application of Saluja-Karpovsky compactors to test responses with many unknowns
inferredcites →https://doi.org/10.1109/vtest.2003.1197673openalex-snapshot
Improving diagnostic resolution of delay faults using path delay fault model
inferredcites →https://doi.org/10.1145/513918.513984openalex-snapshot
Effective diagnostics through interval unloads in a BIST environment
inferredcites →https://doi.org/10.1145/775832.775920openalex-snapshot
Parameter variations and impact on circuits and microarchitecture
inferredcites →https://doi.org/10.1145/775832.776001openalex-snapshot
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models
inferredcites →https://doi.org/10.5555/224841.224878openalex-snapshot
On adaptive diagnostic test generation
inferredcites →https://doi.org/10.5555/266388.266552openalex-snapshot
A deductive technique for diagnosis of bridging faults
inferredcites →https://doi.org/10.5555/367072.367105openalex-snapshot
Diagnosis for scan-based BIST: reaching deep into the signatures
inferredcites →https://doi.org/10.5555/789083.1022745openalex-snapshot
Non-Enumerative Path Delay Fault Diagnosis
inferredcites →https://doi.org/10.5555/789083.1022746openalex-snapshot
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
inferredcites →https://doi.org/10.5555/882452.874345openalex-snapshot
Gate Level Fault Diagnosis in Scan-Based BIST
inferredcites →https://doi.org/10.5555/968879.969201openalex-snapshot
Impact of test point insertion on silicon area and timing during layout
inferredcites →https://doi.org/10.5555/968879.969216openalex-snapshot
Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10836-009-5109-3openalex-snapshot
Adaptive Debug and Diagnosis Without Fault Dictionaries
inferred← citeshttps://doi.org/10.1016/j.micpro.2008.03.006openalex-snapshot
Embedded fault diagnosis in digital systems with BIST
inferred← citeshttps://doi.org/10.1109/asqed.2009.5206232openalex-snapshot
Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networks
inferred← citeshttps://doi.org/10.1109/delta.2006.79openalex-snapshot
Some common aspects of design validation, debug and diagnosis
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341530openalex-snapshot
Fault Diagnosis in Integrated Circuits with BIST
inferred← citeshttps://doi.org/10.1109/dsd.2007.56openalex-snapshot
Fault Diagnosis in Integrated Circuits with BIST
inferred← citeshttps://doi.org/10.1109/ets.2007.9openalex-snapshot
Adaptive Debug and Diagnosis without Fault Dictionaries
inferred← citeshttps://doi.org/10.1109/ets.2008.40openalex-snapshot
Adaptive Debug and Diagnosis without Fault Dictionaries
inferred← citeshttps://doi.org/10.1109/icmel.2008.4559311openalex-snapshot
Embedded diagnosis in digital systems
inferred← citeshttps://doi.org/10.1109/mtv.2008.14openalex-snapshot
A New Methodology for the Test of SoCs and for Analyzing Elusive Failures
inferred← citeshttps://doi.org/10.1109/test.2006.297719openalex-snapshot
Signature Analyzer Design for Yield Learning Support
inferred← citeshttps://doi.org/10.18419/opus-3585openalex-snapshot
Self-diagnosis in Network-on-Chips
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