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Adaptive Debug and Diagnosis without Fault Dictionaries

https://doi.org/10.1109/ets.2007.9

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-73910-1openalex-snapshot

Testmustergenerierung und Fehlersimulation in digitalen Schaltungen mit hoher Komplexität

inferredcites →https://doi.org/10.1023/a:1021948013402openalex-snapshot

Design Error Diagnosis with Re-Synthesis in Combinational Circuits

inferredcites →https://doi.org/10.1109/43.748164openalex-snapshot

Creating small fault dictionaries [logic circuit fault diagnosis]

inferredcites →https://doi.org/10.1109/54.32421openalex-snapshot

Failure diagnosis of structured VLSI

inferredcites →https://doi.org/10.1109/delta.2006.79openalex-snapshot

Some common aspects of design validation, debug and diagnosis

inferredcites →https://doi.org/10.1109/ets.2005.26openalex-snapshot

From Embedded Test to Embedded Diagnosis

inferredcites →https://doi.org/10.1109/ets.2005.35openalex-snapshot

Stuck-Open Fault Diagnosis with Stuck-At Model

inferredcites →https://doi.org/10.1109/icasic.2003.1277481openalex-snapshot

Assertion-based verification for SoC designs

inferredcites →https://doi.org/10.1109/iccad.1992.279361openalex-snapshot

On the generation of small dictionaries for fault location

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On adaptive diagnostic test generation

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Fault equivalence and diagnostic test generation using ATPG

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Accelerating functional simulation for processor based designs

inferredcites →https://doi.org/10.1109/mdt.2006.52openalex-snapshot

Test consideration for nanometer-scale CMOS circuits

inferredcites →https://doi.org/10.1109/tcad.2003.816206openalex-snapshot

Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT)

inferredcites →https://doi.org/10.1109/test.1990.114104openalex-snapshot

Diagnosing CMOS bridging faults with stuck-at fault dictionaries

inferredcites →https://doi.org/10.1109/test.1997.639632openalex-snapshot

Signature analysis for IC diagnosis and failure analysis

inferredcites →https://doi.org/10.1109/test.1998.743308openalex-snapshot

Probabilistic mixed-model fault diagnosis

inferredcites →https://doi.org/10.1109/test.1998.743310openalex-snapshot

Modeling the unknown! Towards model-independent fault and error diagnosis

inferredcites →https://doi.org/10.1109/test.2000.894285openalex-snapshot

Fault distinguishing pattern generation

inferredcites →https://doi.org/10.1109/test.2001.966644openalex-snapshot

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

inferredcites →https://doi.org/10.1109/test.2002.1041768openalex-snapshot

An effective diagnosis method to support yield improvement

inferredcites →https://doi.org/10.1109/test.2006.297627openalex-snapshot

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior

inferredcites →https://doi.org/10.1109/test.2006.297647openalex-snapshot

Diagnostic Test Generation for Arbitrary Faults

inferredcites →https://doi.org/10.1109/test.2006.297661openalex-snapshot

Improving Precision Using Mixed-level Fault Diagnosis

inferredcites →https://doi.org/10.1109/test.2006.297671openalex-snapshot

Debug of the CELL Processor: Moving the Lab into Silicon

inferredcites →https://doi.org/10.1109/vtest.1994.292283openalex-snapshot

CMOS bridging fault modeling

inferredcites →https://doi.org/10.1109/vtest.1996.510854openalex-snapshot

Full fault dictionary storage based on labeled tree encoding

inferredcites →https://doi.org/10.1145/1146909.1146959openalex-snapshot

Reliability challenges for 45nm and beyond

inferredcites →https://doi.org/10.1145/800139.804514openalex-snapshot

Fault diagnosis based on effect-cause analysis

inferredcites →https://doi.org/10.5555/224841.224878openalex-snapshot

On adaptive diagnostic test generation

inferredcites →https://doi.org/10.5555/304032.304116openalex-snapshot

On the generation of small dictionaries for fault location

inferredcites →https://doi.org/10.5555/789083.1022746openalex-snapshot

Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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On Test Generation for Microprocessors for Extended Class of Functional Faults

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Machine Learning Support for Diagnosis of Analog Circuits

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Partition-Based Faults Diagnosis of a VLIW Processor

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Employing Test Suites for Verilog Fault Localization

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Generalized Fault Modeling for Logic Diagnosis

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Adaptive Debug and Diagnosis Without Fault Dictionaries

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High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

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Test vector chains for increased resolution and reduced storage of diagnostic tests

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Physical‐aware systematic multiple defect diagnosis

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Improving the accuracy of defect diagnosis by adding and removing tests

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Combined pseudo-exhaustive and deterministic testing of array multipliers

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Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networks

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Diagnosis of Multiple Physical Defects Using Logic Fault Models

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A Comprehensive System-on-Chip Logic Diagnosis

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Diagnostic Test of Robust Circuits

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Embedded Test for Highly Accurate Defect Localization

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Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns

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Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models

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PADLOC: Physically-Aware Defect Localization and Characterization

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A tool for random test generation targeting high diagnostic resolution

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Scan Chain Organization for Embedded Diagnosis

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Selection of a fault model for fault diagnosis based on unique responses

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A diagnosis algorithm for extreme space compaction

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BISD: Scan-based Built-In self-diagnosis

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Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs

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Classes of difficult-to-diagnose transition fault clusters

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Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests

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Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

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A fault-simulation-based approach for logic diagnosis

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Bridge Defect Diagnosis for Multiple-Voltage Design

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On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

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Structural In-Field Diagnosis for Random Logic Circuits

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Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test

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LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology

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Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

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Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference

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OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis

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Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach

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A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns

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Grading Defects: Evaluating Approximate Circuits for Error-Tolerant Systems

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Novel Approach for Multiple Arbitrary Faults Diagnosis in Combinational Circuits

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Test Patterns for Verilog Design Error Localization

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A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects

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Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults

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Diagnosis of Multiple-Voltage Design With Bridge Defect

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Functional Broadside Tests for Multistep Defect Diagnosis

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Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests

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New Targets for Diagnostic Test Generation

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Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

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Selection of a Fault Model for Fault Diagnosis Based on Unique Responses

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Resolution of Diagnosis Based on Transition Faults

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Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs

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Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects

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On the development of diagnostic test programs for VLIW processors

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A Deterministic-Statistical Multiple-Defect Diagnosis Methodology

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Scan chain organization for embedded diagnosis

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Diagnosis of transition fault clusters

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Fault diagnosis of VLSI designs

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Diagnosis Of VLSI circuit defects

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Simulation of realistic defects for validating test- and diagnosis-algorithms

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Adaptive simulationsbasierte Diagnose von Verzögerungsfehlern in kombinatorischen Schaltungen

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Analog Hardware Fault Diagnosis

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Diagnostic de pannes électriques dans les systèmes logiques

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Techniques d’apprentissage pour la caractérisation de bibliothèques de cellules en vue du test et du diagnostic de circuits intégrés.

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