On the public citation graph

Structural In-Field Diagnosis for Random Logic Circuits

https://doi.org/10.1109/ets.2011.25

0 signed · 46 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10836-009-5109-3openalex-snapshot

Adaptive Debug and Diagnosis Without Fault Dictionaries

inferredcites →https://doi.org/10.1016/s0167-9260(98)00021-2openalex-snapshot

BIST for systems-on-a-chip

inferredcites →https://doi.org/10.1109/12.780879openalex-snapshot

Diagnosis of scan cells in BIST environment

inferredcites →https://doi.org/10.1109/54.32421openalex-snapshot

Failure diagnosis of structured VLSI

inferredcites →https://doi.org/10.1109/dac.2002.1012630openalex-snapshot

Effective diagnostics through interval unloads in a BIST environment

inferredcites →https://doi.org/10.1109/date.2002.998301openalex-snapshot

Gate level fault diagnosis in scan-based BIST

inferredcites →https://doi.org/10.1109/date.2002.998302openalex-snapshot

An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST environment

inferredcites →https://doi.org/10.1109/date.2004.1269075openalex-snapshot

Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes

inferredcites →https://doi.org/10.1109/date.2010.5456997openalex-snapshot

BISD: Scan-based Built-In self-diagnosis

inferredcites →https://doi.org/10.1109/ets.2007.9openalex-snapshot

Adaptive Debug and Diagnosis without Fault Dictionaries

inferredcites →https://doi.org/10.1109/tcad.2004.823341openalex-snapshot

X-Compact: An Efficient Response Compaction Technique

inferredcites →https://doi.org/10.1109/tcad.2005.844111openalex-snapshot

Finite memory test response compactors for embedded test applications

inferredcites →https://doi.org/10.1109/test.2006.297627openalex-snapshot

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior

inferredcites →https://doi.org/10.1109/test.2006.297661openalex-snapshot

Improving Precision Using Mixed-level Fault Diagnosis

inferredcites →https://doi.org/10.1109/test.2006.297720openalex-snapshot

Signature Based Diagnosis for Logic BIST

inferredcites →https://doi.org/10.1109/test.2007.4437576openalex-snapshot

X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR

inferredcites →https://doi.org/10.1109/test.2007.4437703openalex-snapshot

Signature based diagnosis for logic BIST

inferredcites →https://doi.org/10.1109/tvlsi.2007.899235openalex-snapshot

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

inferredcites →https://doi.org/10.1109/vtest.2000.843830openalex-snapshot

A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains

inferredcites →https://doi.org/10.1109/vtest.2003.1197640openalex-snapshot

Application of Saluja-Karpovsky compactors to test responses with many unknowns

inferredcites →https://doi.org/10.1109/vts.2009.43openalex-snapshot

Restrict Encoding for Mixed-Mode BIST

inferredcites →https://doi.org/10.1145/513918.513984openalex-snapshot

Effective diagnostics through interval unloads in a BIST environment

inferredcites →https://doi.org/10.1145/800139.804514openalex-snapshot

Fault diagnosis based on effect-cause analysis

inferredcites →https://doi.org/10.5555/1870926.1871225openalex-snapshot

BISD: scan-based built-in self-diagnosis

inferredcites →https://doi.org/10.5555/882452.874343openalex-snapshot

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment

inferredcites →https://doi.org/10.5555/882452.874345openalex-snapshot

Gate Level Fault Diagnosis in Scan-Based BIST

inferredcites →https://doi.org/10.5555/968879.969216openalex-snapshot

Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-19639-3_4openalex-snapshot

Machine Learning Support for Logic Diagnosis and Defect Classification

inferred← citeshttps://doi.org/10.1007/s10836-014-5477-1openalex-snapshot

Adaptive Bayesian Diagnosis of Intermittent Faults

inferred← citeshttps://doi.org/10.1109/ats.2011.55openalex-snapshot

Diagnostic Test of Robust Circuits

inferred← citeshttps://doi.org/10.1109/ats.2016.46openalex-snapshot

A Neural-Network-Based Fault Classifier

inferred← citeshttps://doi.org/10.1109/ats47505.2019.000-4openalex-snapshot

A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures

inferred← citeshttps://doi.org/10.1109/ddecs.2012.6219080openalex-snapshot

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores

inferred← citeshttps://doi.org/10.1109/ddecs.2017.7934586openalex-snapshot

Logic testing with test-per-clock pattern loading and improved diagnostic abilities

inferred← citeshttps://doi.org/10.1109/dft.2014.6962072openalex-snapshot

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults

inferred← citeshttps://doi.org/10.1109/ets.2012.6233025openalex-snapshot

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test

inferred← citeshttps://doi.org/10.1109/ets.2014.6847795openalex-snapshot

Systematic generation of diagnostic software-based self-test routines for processor components

inferred← citeshttps://doi.org/10.1109/ets.2014.6847796openalex-snapshot

Diagnosis of multiple faults with highly compacted test responses

inferred← citeshttps://doi.org/10.1109/ets61313.2024.10567295openalex-snapshot

Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations

inferred← citeshttps://doi.org/10.1109/latw.2012.6261229openalex-snapshot

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test

inferred← citeshttps://doi.org/10.1109/latw.2013.6562676openalex-snapshot

Towards an automatic generation of diagnostic in-field SBST for processor components

inferred← citeshttps://doi.org/10.1109/latw.2016.7483336openalex-snapshot

A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors

inferred← citeshttps://doi.org/10.1109/vts56346.2023.10140109openalex-snapshot

A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin

inferred← citeshttps://doi.org/10.1145/2593069.2602971openalex-snapshot

Advanced Diagnosis

inferred← citeshttps://doi.org/10.18419/opus-2972openalex-snapshot

Efficient location-based logic diagnosis of digital circuits

inferred← citeshttps://doi.org/10.18419/opus-9199openalex-snapshot

Machine learning support for logic diagnosis

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.