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Cooperative Caching with Keep-Me and Evict-Me
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-24644-2_6openalex-snapshot
Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation
inferredcites →https://doi.org/10.1109/12.752656openalex-snapshot
An algorithm for optimally exploiting spatial and temporal locality in upper memory levels
inferredcites →https://doi.org/10.1109/2.689677openalex-snapshot
Smarter memory: improving bandwidth for streamed references
inferredcites →https://doi.org/10.1109/71.86110openalex-snapshot
An implementation of interprocedural bounded regular section analysis
inferredcites →https://doi.org/10.1109/hpca.1996.501190openalex-snapshot
Predictive sequential associative cache
inferredcites →https://doi.org/10.1109/hpca.1997.569689openalex-snapshot
Performance characterization of the Pentium Pro processor
inferredcites →https://doi.org/10.1109/hpca.1999.744334openalex-snapshot
Impulse: building a smarter memory controller
inferredcites →https://doi.org/10.1109/hpca.2000.824338openalex-snapshot
Modified LRU policies for improving second-level cache behavior
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/iccd.1998.727028openalex-snapshot
The Alpha 21264 microprocessor architecture
inferredcites →https://doi.org/10.1109/isca.1989.714547openalex-snapshot
Inexpensive Implementations Of Set-Associativity
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/isca.1993.698559openalex-snapshot
Column-associative Caches: A Technique For Reducing The Miss Rate Of Direct-mapped Caches
inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1109/isca.1995.524567openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1109/isca.2000.854395openalex-snapshot
Clock rate versus IPC: the end of the road for conventional microarchitectures
inferredcites →https://doi.org/10.1109/micro.1997.645797openalex-snapshot
Run-time spatial locality detection and optimization
inferredcites →https://doi.org/10.1109/pact.1998.727266openalex-snapshot
A matrix-based approach to the global locality optimization problem
inferredcites →https://doi.org/10.1109/pact.2002.1106018openalex-snapshot
Using the compiler to improve cache replacement decisions
inferredcites →https://doi.org/10.1145/125826.125932openalex-snapshot
An effective on-chip preloading scheme to reduce data access penalty
inferredcites →https://doi.org/10.1145/135226.135233openalex-snapshot
A practical algorithm for exact array dependence analysis
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/166955.166974openalex-snapshot
Efficient simulation of caches under optimal replacement with applications to miss characterization
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/223982.224437openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1145/225830.224437openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/233561.233564openalex-snapshot
Improving data locality with loop transformations
inferredcites →https://doi.org/10.1145/277830.277941openalex-snapshot
Utilizing reuse information in data cache management
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/291069.291051openalex-snapshot
Precise miss analysis for program transformations with caches of arbitrary associativity
inferredcites →https://doi.org/10.1145/291069.291053openalex-snapshot
Capturing dynamic memory reference behavior with adaptive cache topology
inferredcites →https://doi.org/10.1145/329466.329484openalex-snapshot
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks
inferredcites →https://doi.org/10.1145/339647.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/342001.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/74925.74941openalex-snapshot
Inexpensive implementations of set-associativity
inferredcites →https://doi.org/10.1147/rd.446.0873openalex-snapshot
POWER3: The next generation of PowerPC processors
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/266800.266806openalex-snapshot
Run-time spatial locality detection and optimization
inferredcites →https://doi.org/10.5555/645989.674328openalex-snapshot
Using the compiler to improve cache replacement decisions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.05.005openalex-snapshot
A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines
inferred← citeshttps://doi.org/10.1109/aspdac.2013.6509584openalex-snapshot
Variability-aware memory management for nanoscale computing
inferred← citeshttps://doi.org/10.1109/ccgrid.2006.33openalex-snapshot
Designing Efficient Cooperative Caching Schemes for Multi-Tier Data-Centers over RDMA-enabled Networks
inferred← citeshttps://doi.org/10.1109/cgo.2011.5764672openalex-snapshot
Link-time optimization for power efficiency in a tagless instruction cache
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446101openalex-snapshot
RADAR: Runtime-assisted dead region management for last-level caches
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/isca.2018.00050openalex-snapshot
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer
inferred← citeshttps://doi.org/10.1109/mic.2020.3026245openalex-snapshot
Rethinking Divide and Conquer—Towards Holistic Interfaces of the Computing Stack
inferred← citeshttps://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferred← citeshttps://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferred← citeshttps://doi.org/10.1109/tc.2015.2395435openalex-snapshot
GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs
inferred← citeshttps://doi.org/10.1145/1254766.1254809openalex-snapshot
Compiler-managed partitioned data caches for low power
inferred← citeshttps://doi.org/10.1145/1273444.1254809openalex-snapshot
Compiler-managed partitioned data caches for low power
inferred← citeshttps://doi.org/10.1145/1629395.1629422openalex-snapshot
Instruction cache locking inside a binary rewriter
inferred← citeshttps://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferred← citeshttps://doi.org/10.1145/2150976.2150993openalex-snapshot
Continuous object access profiling and optimizations to overcome the memory wall and bloat
inferred← citeshttps://doi.org/10.1145/2159430.2159443openalex-snapshot
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs
inferred← citeshttps://doi.org/10.1145/2189750.2150993openalex-snapshot
Continuous object access profiling and optimizations to overcome the memory wall and bloat
inferred← citeshttps://doi.org/10.1145/2248487.2150993openalex-snapshot
Continuous object access profiling and optimizations to overcome the memory wall and bloat
inferred← citeshttps://doi.org/10.1145/2700100openalex-snapshot
Instruction-Cache Locking for Improving Embedded Systems Performance
inferred← citeshttps://doi.org/10.1145/2814270.2814290openalex-snapshot
Performance problems you can fix: a dynamic analysis of memoization opportunities
inferred← citeshttps://doi.org/10.1145/2858965.2814290openalex-snapshot
Performance problems you can fix: a dynamic analysis of memoization opportunities
inferred← citeshttps://doi.org/10.1145/3234337openalex-snapshot
Global Dead-Block Management for Task-Parallel Programs
inferred← citeshttps://doi.org/10.1145/3505250openalex-snapshot
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations
inferred← citeshttps://doi.org/10.5821/dissertation-2117-335422openalex-snapshot
Runtime-assisted optimizations in the on-chip memory hierarchy
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