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Sampling Dead Block Prediction for Last-Level Caches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/71.298211openalex-snapshot
Massively parallel algorithms for trace-driven cache simulations
inferredcites →https://doi.org/10.1109/iccd.2007.4601909openalex-snapshot
Cache replacement based on reuse-distance prediction
inferredcites →https://doi.org/10.1109/interact.2005.7openalex-snapshot
Cooperative Caching with Keep-Me and Evict-Me
inferredcites →https://doi.org/10.1109/isca.2006.5openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferredcites →https://doi.org/10.1109/pact.2002.1106018openalex-snapshot
Using the compiler to improve cache replacement decisions
inferredcites →https://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferredcites →https://doi.org/10.1145/1054943.1054949openalex-snapshot
Memory coherence activity prediction in commercial workloads
inferredcites →https://doi.org/10.1145/1061267.1061271openalex-snapshot
IATAC: a smart predictor to turn-off L2 cache lines
inferredcites →https://doi.org/10.1145/1150019.1136501openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1454115.1454145openalex-snapshot
Adaptive insertion policies for managing shared caches
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferredcites →https://doi.org/10.1145/264107.264211openalex-snapshot
Trading conflict and capacity aliasing in conditional branch predictors
inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot
Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/384285.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/545214.545239openalex-snapshot
Timekeeping in the memory system
inferredcites →https://doi.org/10.1145/781027.781076openalex-snapshot
Using SimPoint for accurate and efficient simulation
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/645989.674328openalex-snapshot
Using the compiler to improve cache replacement decisions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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RUE: A caching method for identifying and managing hot data by leveraging resource utilization efficiency
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Evaluating Cache Line Behavior Predictors for Energy Efficient Processors
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Reducing Timing Discrepancy for Energy-Efficient On-Chip Memory Architectures at Low-Voltage Mode
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Periodic learning-based region selection for energy-efficient MLC STT-RAM cache
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Near-optimal replacement policies for shared caches in multicore processors
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CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks
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Retention Benefit Based Intelligent Cache Replacement
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Applying machine learning to enhance the cache performance using reuse distance
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Reuse locality aware cache partitioning for last-level cache
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A fault-tolerant last level cache for CMPs operating at ultra-low voltage
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ReD: A reuse detector for content selection in exclusive shared last-level caches
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Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme
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Early miss prediction based periodic cache bypassing for high performance GPUs
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Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures
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ECAP: energy‐efficient caching for prefetch blocks in tiled chip multiprocessors
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Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches
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An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators
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A Future-Oriented Cache Management for Mobile Games
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RedCache: Reduced DRAM Caching
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Global Priority Table for Last-Level Caches
inferred← citeshttps://doi.org/10.1109/eiect64462.2024.10866499openalex-snapshot
Branch-Target Correlation to Resolve Sub-Trace Aliasing in Dead Block Predictor
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Decoupled dynamic cache segmentation
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RECAP: A region-based cure for the common cold (cache)
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522314openalex-snapshot
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835921openalex-snapshot
Locality-aware data replication in the Last-Level Cache
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835933openalex-snapshot
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835944openalex-snapshot
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture
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Improving cache performance using read-write partitioning
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056023openalex-snapshot
Coordinated static and dynamic cache bypassing for GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446065openalex-snapshot
Minimal disturbance placement and promotion
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446067openalex-snapshot
Modeling cache performance beyond LRU
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446101openalex-snapshot
RADAR: Runtime-assisted dead region management for last-level caches
inferred← citeshttps://doi.org/10.1109/hpca.2017.43openalex-snapshot
Maximizing Cache Performance Under Uncertainty
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PM3: Power Modeling and Power Management for Processing-in-Memory
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FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00028openalex-snapshot
Domain-Specialized Cache Management for Graph Analytics
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00060openalex-snapshot
Stream Floating: Enabling Proactive and Decentralized Cache Optimizations
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00062openalex-snapshot
P-OPT: Practical Optimal Cache Replacement for Graph Analytics
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00048openalex-snapshot
Effective Mimicry of Belady’s MIN Policy
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071033openalex-snapshot
ACIC: Admission-Controlled Instruction Cache
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A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering
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CHROME: Concurrency-Aware Holistic Cache Management Framework with Online Reinforcement Learning
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From Optimal to Practical: Efficient Micro-op Cache Replacement Policies for Data Center Applications
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BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism
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Flow Correlator: A Flow Table Cache Management Strategy
inferred← citeshttps://doi.org/10.1109/icccnt51525.2021.9580059openalex-snapshot
WeiSub: Weighted Subset-based Cache Replacement Policy for Last Level Caches
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Improving inclusive cache performance with two-level eviction priority
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Power gating with block migration in chip-multiprocessor last-level caches
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657055openalex-snapshot
FreshCache: Statically and dynamically exploiting dataless ways
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ReMAP: Reuse and memory access cost aware eviction policy for last level cache management
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Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache
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Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUs
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“Stubborn” strategy to mitigate remaining cache misses
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To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
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SpecLock: Speculative Lock Forwarding
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Characterization and Throttling-Based Mitigation of Memory Interference for Heterogeneous Smartphones
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ID-cache: instruction and memory divergence based cache management for GPUs
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A Closer Look at Lightweight Graph Reordering
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Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior
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Characterizing the impact of last-level cache replacement policies on big-data workloads
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Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.96openalex-snapshot
OWBP: Flash-Aware Offline Write Buffer Policy
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Improving writeback efficiency with decoupled last-write prediction
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Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement
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Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies
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Rethinking Belady's Algorithm to Accommodate Prefetching
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Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache
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Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer
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Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
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Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
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Bumper: Hinting Instruction Usefulness for Robust Unified Caches
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Enhancing Instruction Prefetching via Cache and TLB Management
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R-Max: Extending BéLáDy's MIN with Prefetching to Bound Realistic Cache Performance
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Write intensity prediction for energy-efficient non-volatile caches
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Address Translation Conscious Caching and Prefetching for High Performance Cache Hierarchy
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Community-based Matrix Reordering for Sparse Linear Algebra Optimization
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Runtime-Assisted Global Cache Management for Task-Based Parallel Programs
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DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches
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Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching
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Improving Cache Management Policies Using Dynamic Reuse Distances
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Adaptive Cache Management for Energy-Efficient GPU Computing
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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
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Perceptron learning for reuse prediction
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Rethinking the Memory Hierarchy for Modern Languages
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CHiRP: Control-Flow History Reuse Prediction
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Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
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Effective Mimicry of Bélády’s MIN Policy
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HyVE: A Hybrid Voting-based Eviction Policy for Caches
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Building expressive, area-efficient coherence directories
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Fine Grain Cache Partitioning Using Per-Instruction Working Blocks
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Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches
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PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback
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Access Pattern Based Re-reference Interval Table for Last Level Cache
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Dynamic Set Stealing to Improve Cache Performance
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TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models
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CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches
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Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
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Statistical Cache Bypassing for Non-Volatile Memory
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Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache
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Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory
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Optimizing Cache Bypassing and Warp Scheduling for GPUs
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Miss Penalty Aware Cache Replacement for Hybrid Memory Systems
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CEGraph: Cache-Efficient Management for Streaming Graph Processing
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An Efficient Hybrid Cache Replacement Policy for Cloud Block Storage
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LvtPPP: Live-Time Protected Pseudopartitioning of Multicore Shared Caches
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A Reliability-Aware Replacement Policy for STT-MRAM Caches in Server-Class Processors
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ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2019.2922660openalex-snapshot
Infection-Based Dead Page Prediction in Hybrid Memory Architecture
inferred← citeshttps://doi.org/10.1109/uv50937.2020.9426214openalex-snapshot
A Novel Prefetching Scheme for Non-Volatile Cache in the AIoT Processor
inferred← citeshttps://doi.org/10.1109/vlsi-soc64688.2025.11421757openalex-snapshot
LiC: Low-Cost Cache Replacement Algorithm for All Cache Levels
inferred← citeshttps://doi.org/10.1142/s0218126621502923openalex-snapshot
LPE: Locality-Based Dead Prediction in Exclusive TLB for Large Coverage
inferred← citeshttps://doi.org/10.1145/2000064.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferred← citeshttps://doi.org/10.1145/2019608.2019613openalex-snapshot
Dynamic access distance driven cache replacement
inferred← citeshttps://doi.org/10.1145/2024723.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferred← citeshttps://doi.org/10.1145/2247684.2247690openalex-snapshot
Rank idle time prediction driven last-level cache writeback
inferred← citeshttps://doi.org/10.1145/2366231.2337195openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferred← citeshttps://doi.org/10.1145/2370816.2370860openalex-snapshot
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches
inferred← citeshttps://doi.org/10.1145/2370816.2370862openalex-snapshot
Optimal bypass monitor for high performance last-level caches
inferred← citeshttps://doi.org/10.1145/2400682.2400697openalex-snapshot
Exploiting reuse locality on inclusive shared last-level caches
inferred← citeshttps://doi.org/10.1145/2451116.2451155openalex-snapshot
To hardware prefetch or not to prefetch?
inferred← citeshttps://doi.org/10.1145/2490301.2451155openalex-snapshot
To hardware prefetch or not to prefetch?
inferred← citeshttps://doi.org/10.1145/2499368.2451155openalex-snapshot
To hardware prefetch or not to prefetch?
inferred← citeshttps://doi.org/10.1145/2534393openalex-snapshot
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
inferred← citeshttps://doi.org/10.1145/2540708.2540733openalex-snapshot
Insertion and promotion for tree-based PseudoLRU last-level caches
inferred← citeshttps://doi.org/10.1145/2541228.2555290openalex-snapshot
Temporal-based multilevel correlating inclusive cache replacement
inferred← citeshttps://doi.org/10.1145/2597652.2597653openalex-snapshot
Block value based insertion policy for high performance last-level caches
inferred← citeshttps://doi.org/10.1145/2597652.2597655openalex-snapshot
Last-level cache deduplication
inferred← citeshttps://doi.org/10.1145/2613908.2613909openalex-snapshot
Adaptive Cache Bypass and Insertion for Many-core Accelerators
inferred← citeshttps://doi.org/10.1145/2677956openalex-snapshot
Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
inferred← citeshttps://doi.org/10.1145/2710019openalex-snapshot
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor
inferred← citeshttps://doi.org/10.1145/2818374openalex-snapshot
Reuse Distance-Based Probabilistic Cache Replacement
inferred← citeshttps://doi.org/10.1145/2818950.2818968openalex-snapshot
Shared Last-Level Caches and The Case for Longer Timeslices
inferred← citeshttps://doi.org/10.1145/2925426.2926282openalex-snapshot
Prefetching Techniques for Near-memory Throughput Processors
inferred← citeshttps://doi.org/10.1145/2971331.2971334openalex-snapshot
Probabilistic Directed Writebacks for Exclusive Caches
inferred← citeshttps://doi.org/10.1145/3123939.3123942openalex-snapshot
Multiperspective reuse prediction
inferred← citeshttps://doi.org/10.1145/3225058.3225104openalex-snapshot
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection
inferred← citeshttps://doi.org/10.1145/3234337openalex-snapshot
Global Dead-Block Management for Task-Parallel Programs
inferred← citeshttps://doi.org/10.1145/3240302.3240416openalex-snapshot
Dynamic fine-grained sparse memory accesses
inferred← citeshttps://doi.org/10.1145/3243176.3243178openalex-snapshot
Synergistic cache layout for reuse and compression
inferred← citeshttps://doi.org/10.1145/3287624.3287633openalex-snapshot
A sharing-aware L1.5D cache for data reuse in GPGPUs
inferred← citeshttps://doi.org/10.1145/3307650.3322207openalex-snapshot
Perceptron-based prefetch filtering
inferred← citeshttps://doi.org/10.1145/3307650.3322246openalex-snapshot
New attacks and defense for encrypted-address cache
inferred← citeshttps://doi.org/10.1145/3323165.3323169openalex-snapshot
Writeback-Aware Caching (Brief Announcement)
inferred← citeshttps://doi.org/10.1145/3352460.3358319openalex-snapshot
Applying Deep Learning to the Cache Replacement Problem
inferred← citeshttps://doi.org/10.1145/3445814.3446752openalex-snapshot
A hierarchical neural model of data prefetching
inferred← citeshttps://doi.org/10.1145/3494538openalex-snapshot
CASHT: Contention Analysis in Shared Hierarchies with Thefts
inferred← citeshttps://doi.org/10.1145/3572839openalex-snapshot
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy
inferred← citeshttps://doi.org/10.1145/3607473openalex-snapshot
Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain
inferred← citeshttps://doi.org/10.1145/3632748openalex-snapshot
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration
inferred← citeshttps://doi.org/10.1145/3650200.3656592openalex-snapshot
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators
inferred← citeshttps://doi.org/10.1145/3653452openalex-snapshot
POEM: Performance Optimization and Endurance Management for Non-volatile Caches
inferred← citeshttps://doi.org/10.1145/3669940.3707247openalex-snapshot
Instruction-Aware Cooperative TLB and Cache Replacement Policies
inferred← citeshttps://doi.org/10.1145/3695053.3730993openalex-snapshot
Light-weight Cache Replacement for Instruction Heavy Workloads
inferred← citeshttps://doi.org/10.1145/3695794.3695803openalex-snapshot
PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC
inferred← citeshttps://doi.org/10.1145/3721286openalex-snapshot
TSN Cache: Exploiting Data Localities in Graph Computing Applications
inferred← citeshttps://doi.org/10.1145/3725843.3756028openalex-snapshot
Drishti: Do Not Forget Slicing While Designing Last-Level Cache Replacement Policies for Many-Core Systems
inferred← citeshttps://doi.org/10.1145/3725843.3756047openalex-snapshot
COSMOS: RL-Enhanced Locality-Aware Counter Cache Optimization for Secure Memory
inferred← citeshttps://doi.org/10.1145/3760746openalex-snapshot
SHARP: SHARing-Aware Cache Writeback byPass
inferred← citeshttps://doi.org/10.1587/elex.12.20150736openalex-snapshot
Applying SVM to data bypass prediction in multi core last-level caches
inferred← citeshttps://doi.org/10.18130/v32600openalex-snapshot
Scrutinizing Resource Utilization for High Performance and Low Energy Computation
inferred← citeshttps://doi.org/10.2197/ipsjjip.27.149openalex-snapshot
A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems
inferred← citeshttps://doi.org/10.2200/s00922ed1v01y201905cac047openalex-snapshot
Cache Replacement Policies
inferred← citeshttps://doi.org/10.23919/date.2017.7927151openalex-snapshot
MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774709openalex-snapshot
Data-Aware Cache Management for Graph Analytics
inferred← citeshttps://doi.org/10.3390/app11073235openalex-snapshot
A Survey of Machine Learning-Based System Performance Optimization Techniques
inferred← citeshttps://doi.org/10.3390/bdcc8100140openalex-snapshot
LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory
inferred← citeshttps://doi.org/10.3390/electronics8060639openalex-snapshot
A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs
inferred← citeshttps://doi.org/10.3390/jlpea6020005openalex-snapshot
A Survey of Cache Bypassing Techniques
inferred← citeshttps://doi.org/10.37099/mtu.dc.etdr/596openalex-snapshot
Modeling Data Center Co-Tenancy Performance Interference
inferred← citeshttps://doi.org/10.48550/arxiv.1808.05024openalex-snapshot
Making Belady-Inspired Replacement Policies More Effective Using Expected Hit Count
inferred← citeshttps://doi.org/10.48550/arxiv.2105.14442openalex-snapshot
Reuse Distance-based Copy-backs of Clean Cache Lines to Lower-level Caches
inferred← citeshttps://doi.org/10.48550/arxiv.2107.13649openalex-snapshot
Reuse Cache for Heterogeneous CPU-GPU Systems
inferred← citeshttps://doi.org/10.48550/arxiv.2109.04621openalex-snapshot
An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5555/2648668.2648724openalex-snapshot
Write intensity prediction for energy-efficient non-volatile caches
inferred← citeshttps://doi.org/10.5555/3195638.3195641openalex-snapshot
Perceptron learning for reuse prediction
inferred← citeshttps://doi.org/10.5821/dissertation-2117-335422openalex-snapshot
Runtime-assisted optimizations in the on-chip memory hierarchy
inferred← citeshttps://doi.org/10.70675/ff9a8713ze4f9z421ez8b99zdfef9781d066openalex-snapshot
Towards compression at all levels in the memory hierarchy
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