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Design and Implementation of an Efficient Stack Machine
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_99openalex-snapshot
Java Technology in an FPGA
inferredcites →https://doi.org/10.1007/978-3-540-39962-9_43openalex-snapshot
JOP: A Java Optimized Processor
inferredcites →https://doi.org/10.1016/0141-9331(90)90099-hopenalex-snapshot
Stack computers: the new wave
inferredcites →https://doi.org/10.1109/54.953277openalex-snapshot
Making Java work for microcontroller applications
inferredcites →https://doi.org/10.1109/isorc.2001.922817openalex-snapshot
Real-time objects on the bare metal: an efficient hardware realization of the Java/sup TM/ Virtual Machine
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware locks for a real‐time Java chip multiprocessor
inferred← citeshttps://doi.org/10.1002/cpe.3963openalex-snapshot
Safety‐critical Java for embedded systems
inferred← citeshttps://doi.org/10.1002/spe.968openalex-snapshot
Worst‐case execution time analysis for a Java processor
inferred← citeshttps://doi.org/10.1007/978-3-030-00470-5_16openalex-snapshot
Hardware Assisted Randomization of Data
inferred← citeshttps://doi.org/10.1007/978-3-642-10265-3_17openalex-snapshot
Towards Time-Predictable Data Caches for Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.10.007openalex-snapshot
Memory management of safety-critical hard real-time systems designed in SystemJ
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.06.001openalex-snapshot
A Java processor architecture for embedded real-time systems
inferred← citeshttps://doi.org/10.1109/acit69831.2026.11700085openalex-snapshot
Abstract Structure of the Computational Process: Component and Identifier Spaces
inferred← citeshttps://doi.org/10.1109/acssc.2010.5757923openalex-snapshot
Time-predictable chip-multiprocessor design
inferred← citeshttps://doi.org/10.1109/date.2006.244146openalex-snapshot
A Time Predictable Java Processor
inferred← citeshttps://doi.org/10.1109/dsd.2012.47openalex-snapshot
EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off
inferred← citeshttps://doi.org/10.1109/ewdts.2014.7027048openalex-snapshot
Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA
inferred← citeshttps://doi.org/10.1109/ismvl.2016.59openalex-snapshot
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules
inferred← citeshttps://doi.org/10.1109/isorc.2009.13openalex-snapshot
Thread-Local Scope Caching for Real-time Java
inferred← citeshttps://doi.org/10.1109/isorc.2013.6913225openalex-snapshot
A time-predictable stack cache
inferred← citeshttps://doi.org/10.1109/isorcw.2015.59openalex-snapshot
Stack Caching Using Split Data Caches
inferred← citeshttps://doi.org/10.1109/rtas.2008.34openalex-snapshot
A Modular Worst-case Execution Time Analysis Tool for Java Processors
inferred← citeshttps://doi.org/10.1109/sies.2008.4577678openalex-snapshot
Performance evaluation of a java chip-multiprocessor
inferred← citeshttps://doi.org/10.1109/stfssd.2009.10openalex-snapshot
Time-predictable Cache Organization
inferred← citeshttps://doi.org/10.1109/trustcom66490.2025.00216openalex-snapshot
DFAFuzz: Fuzzing for Embedded JavaScript Virtual Machines with Type-Directed DFA
inferred← citeshttps://doi.org/10.1145/1167999.1168010openalex-snapshot
A co-design strategy for embedded Java applications based on a hardware interface with invocation semantics
inferred← citeshttps://doi.org/10.1145/1167999.1168013openalex-snapshot
Exact roots for a real-time garbage collector
inferred← citeshttps://doi.org/10.1145/1196636.1196638openalex-snapshot
Hardware support for detecting illegal references in a multiapplication real-time Java environment
inferred← citeshttps://doi.org/10.1145/1814539.1814548openalex-snapshot
A real-time Java chip-multiprocessor
inferred← citeshttps://doi.org/10.1145/2629649openalex-snapshot
A Java Processor IP Design for Embedded SoC
inferred← citeshttps://doi.org/10.1145/2997465.2997488openalex-snapshot
A Software Managed Stack Cache for Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3397537.3397563openalex-snapshot
Running parallel bytecode interpreters on heterogeneous hardware
inferred← citeshttps://doi.org/10.1145/3568973openalex-snapshot
RegCPython: A Register-based Python Interpreter for Better Performance
inferred← citeshttps://doi.org/10.1155/2009/758480openalex-snapshot
Time-Predictable Computer Architecture
inferred← citeshttps://doi.org/10.23939/acps2016.02.093openalex-snapshot
Parallel Ordered-Access Machine Computational Model and Architecture
inferred← citeshttps://doi.org/10.23939/csn2018.905.088openalex-snapshot
Combining the models of computation by the multitype identifiers of the computer facilities components
inferred← citeshttps://doi.org/10.32657/10356/68990openalex-snapshot
The iDEA architecture-focused FPGA soft processor
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