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The Effect of Virtual Channel Organization on the Performance of Interconnection Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jpdc.1994.1132openalex-snapshot
A Comprehensive Analytical Model for Wormhole Routing in Multicomputer Systems
inferredcites →https://doi.org/10.1007/3-540-55599-4_115openalex-snapshot
Improving the efficiency of virtual channels with time-dependent selection functions
inferredcites →https://doi.org/10.1007/3-540-56320-2_53openalex-snapshot
Mosaic C: An experimental fine-grain multicomputer
inferredcites →https://doi.org/10.1016/s0166-5316(00)00049-3openalex-snapshot
An accurate analytical model of adaptive wormhole routing in k-ary n-cubes interconnection networks
inferredcites →https://doi.org/10.1016/s0167-8191(01)00146-6openalex-snapshot
Performance analysis of adaptive wormhole routing in a two-dimensional torus
inferredcites →https://doi.org/10.1109/12.53599openalex-snapshot
Performance analysis of k-ary n-cube interconnection networks
inferredcites →https://doi.org/10.1109/2.191995openalex-snapshot
A survey of wormhole routing techniques in direct networks
inferredcites →https://doi.org/10.1109/40.87568openalex-snapshot
iWarp: a 100-MOPS, LIW microprocessor for multicomputers
inferredcites →https://doi.org/10.1109/65.580917openalex-snapshot
A survey and comparison of wormhole routing techniques in a mesh networks
inferredcites →https://doi.org/10.1109/71.277793openalex-snapshot
Performance analysis of mesh interconnection networks with deterministic routing
inferredcites →https://doi.org/10.1109/71.663877openalex-snapshot
A cost and speed model for k-ary n-cube wormhole routers
inferredcites →https://doi.org/10.1109/71.97897openalex-snapshot
Limits on interconnection network performance
inferredcites →https://doi.org/10.1109/cmpcon.1993.289660openalex-snapshot
Cray T3D: a new dimension for Cray Research
inferredcites →https://doi.org/10.1109/ipdps.2005.427openalex-snapshot
The Effect of Virtual Channel Organization on the Performance of Interconnection Networks
inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot
Virtual-channel flow control
inferredcites →https://doi.org/10.1109/pact.1997.644004openalex-snapshot
Empirical evaluation of deterministic and adaptive routing with constant-area routers
inferredcites →https://doi.org/10.1109/pccc.2000.830309openalex-snapshot
A performance evaluation of fully adaptive wormhole routing including selection function choice
inferredcites →https://doi.org/10.1109/tc.1985.6312198openalex-snapshot
“Hot spot” contention and combining in multistage interconnection networks
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1145/509593.509632openalex-snapshot
Performance of the CRAY T3E multiprocessor
inferredcites →https://doi.org/10.5555/522659.825658openalex-snapshot
Empirical evaluation of deterministic and adaptive routing with constant-area routers
inferredcites →https://doi.org/10.7551/mitpress/1425.003.0025openalex-snapshot
Performance Analysis of k-ary n-cube Interconnection Networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-0-387-09655-1_18openalex-snapshot
Self-optimized Routing in a Network on-a-Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-89985-3_12openalex-snapshot
Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture
inferred← citeshttps://doi.org/10.1007/978-90-481-3031-3_3openalex-snapshot
ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]
inferred← citeshttps://doi.org/10.1007/s11227-018-2694-xopenalex-snapshot
Application-aware NoC management in GPUs multitasking
inferred← citeshttps://doi.org/10.1007/s11276-021-02882-xopenalex-snapshot
DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing
inferred← citeshttps://doi.org/10.1016/b978-0-12-800979-6.00003-2openalex-snapshot
Dynamic virtual channel routers with congestion awareness††Part of this research was first presented at the 45th Design Automation Conference (DAC-2008) [19] and the 29th International Conference of Computer Design (ICCD-2011) [33].
inferred← citeshttps://doi.org/10.1016/j.micpro.2011.05.002openalex-snapshot
Designing power and performance optimal application-specific Network-on-Chip architectures
inferred← citeshttps://doi.org/10.1109/cisis.2008.46openalex-snapshot
Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers
inferred← citeshttps://doi.org/10.1109/iccd.2011.6081407openalex-snapshot
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378673openalex-snapshot
Adaptive Backpressure: Efficient buffer management for on-chip networks
inferred← citeshttps://doi.org/10.1109/icess.2009.89openalex-snapshot
An Enhanced Fault-Tolerant Routing Algorithm for Mesh Network-on-Chip
inferred← citeshttps://doi.org/10.1109/icinis.2010.78openalex-snapshot
A Virtual Channel Calculation Algorithm for Application Specific On-chip Networks
inferred← citeshttps://doi.org/10.1109/icm.2017.8268864openalex-snapshot
Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip
inferred← citeshttps://doi.org/10.1109/icsict.2012.6467882openalex-snapshot
Evaluation of buffer organizations for network-on-chip
inferred← citeshttps://doi.org/10.1109/innovations.2008.4781684openalex-snapshot
Power efficient switches with dynamic virtual channel allocation for network-on-chips
inferred← citeshttps://doi.org/10.1109/isca.2008.14openalex-snapshot
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
inferred← citeshttps://doi.org/10.1109/ises54909.2022.00126openalex-snapshot
Impact analysis of virtual channels and Buffers on different Network-on-chip configurations
inferred← citeshttps://doi.org/10.1109/isqed.2007.169openalex-snapshot
Virtual Channels Planning for Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/itng.2009.182openalex-snapshot
Processor Allocation Problem for NoC-Based Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/jec-ecc.2012.6186980openalex-snapshot
Congestion mitigation using flexible router architecture for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/micro.2006.50openalex-snapshot
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
inferred← citeshttps://doi.org/10.1109/nocs.2010.25openalex-snapshot
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip
inferred← citeshttps://doi.org/10.1109/nocs.2013.6558415openalex-snapshot
A speculative arbiter design to enable high-frequency many-VC router in NoCs
inferred← citeshttps://doi.org/10.1109/paap.2014.25openalex-snapshot
Design and Evaluation of Dynamically-Allocated Multi-queue Buffers with Multiple Packets for NoC Routers
inferred← citeshttps://doi.org/10.1109/pdp.2011.37openalex-snapshot
A Wireless Network-on-Chip Design for Multicore Platforms
inferred← citeshttps://doi.org/10.1109/tc.2008.77openalex-snapshot
Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
inferred← citeshttps://doi.org/10.1109/tcad.2019.2907909openalex-snapshot
Enhancing Network-on-Chip Performance by Reusing Trace Buffers
inferred← citeshttps://doi.org/10.1109/tpds.2014.2351816openalex-snapshot
Heterogeneous NoC Router Architecture
inferred← citeshttps://doi.org/10.1109/tpds.2018.2812164openalex-snapshot
Game-Based Thermal-Delay-Aware Adaptive Routing (GTDAR) for Temperature-Aware 3D Network-on-Chip Systems
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2015.7314416openalex-snapshot
Traffic-aware buffer reconfiguration in on-chip networks
inferred← citeshttps://doi.org/10.1109/vlsi.design.2009.87openalex-snapshot
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
inferred← citeshttps://doi.org/10.1109/vlsisoc.2011.6081596openalex-snapshot
Two-levels of adaptive buffer for virtual channel router in NoCs
inferred← citeshttps://doi.org/10.1109/wamca.2012.11openalex-snapshot
Optimal Virtual Channel Insertion for Contention Alleviation and Deadlock Avoidance in Custom NoCs
inferred← citeshttps://doi.org/10.1142/s0129626408003363openalex-snapshot
ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE
inferred← citeshttps://doi.org/10.1145/1391469.1391630openalex-snapshot
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
inferred← citeshttps://doi.org/10.1145/1531542.1531658openalex-snapshot
Reliability aware NoC router architecture using input channel buffer sharing
inferred← citeshttps://doi.org/10.1166/jolpe.2009.1038openalex-snapshot
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips
inferred← citeshttps://doi.org/10.24200/tjer.vol7iss2pp80-90openalex-snapshot
Analysis of Buffer Arrangements in Low and High Dimensional Networks
inferred← citeshttps://doi.org/10.2478/v10006-011-0029-7openalex-snapshot
Energy characteristic of a processor allocator and a network-on-chip
inferred← citeshttps://doi.org/10.26634/jse.4.3.1112openalex-snapshot
Fault Tolerance and Reliability of Mesh Multi-computer Networks � A Review
inferred← citeshttps://doi.org/10.32920/ryerson.14649366openalex-snapshot
Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures
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Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures
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Processor allocator for chip multiprocessors
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Design Space Exploration for Networks On-chip
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