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ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Virtual cut-through: A new computer communication switching technique
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Evaluation of queue designs for true fully adaptive routers
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Performance analysis of buffering schemes in wormhole routers
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Networks on chips: a new SoC paradigm
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A delay model for router microarchitectures
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High-level modeling and design of asynchronous interface logic
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A new theory of deadlock-free adaptive routing in wormhole networks
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Traffic analysis for on-chip networks design of multimedia applications
inferredcites →https://doi.org/10.1109/date.2005.40openalex-snapshot
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
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A delay model and speculative architecture for pipelined routers
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Dynamic voltage scaling with links for power optimization of interconnection networks
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Application-specific buffer space allocation for networks-on-chip router design
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The design and implementation of a multiqueue buffer for VLSI communication switches
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Circular buffered switch design with wormhole routing and virtual channels
inferredcites →https://doi.org/10.1109/ipdps.2003.1213133openalex-snapshot
BLAM: a high-performance routing algorithm for virtual cut-through networks
inferredcites →https://doi.org/10.1109/ipdps.2005.427openalex-snapshot
The Effect of Virtual Channel Organization on the Performance of Interconnection Networks
inferredcites →https://doi.org/10.1109/isca.1988.5245openalex-snapshot
High-performance multiqueue buffers for VLSI communication switches
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Virtual-channel flow control
inferredcites →https://doi.org/10.1109/isca.2003.1207000openalex-snapshot
GOAL: a load-balanced adaptive routing algorithm for torus networks
inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/isca.2005.34openalex-snapshot
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
inferredcites →https://doi.org/10.1109/isvlsi.2003.1183347openalex-snapshot
Networks-on-chip: the quest for on-chip fault-tolerant communication
inferredcites →https://doi.org/10.1109/lpe.2003.1231841openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1109/micro.2004.35openalex-snapshot
Thermal Modeling, Characterization and Management of On-Chip Networks
inferredcites →https://doi.org/10.1109/superc.1994.344337openalex-snapshot
Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.1145/1077603.1077692openalex-snapshot
Replacing global wires with an on-chip network
inferredcites →https://doi.org/10.1145/1080695.1070004openalex-snapshot
Interconnections in Multi-Core Architectures
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/513918.514116openalex-snapshot
Traffic analysis for on-chip networks design of multimedia applications
inferredcites →https://doi.org/10.1145/514049.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/633625.52439openalex-snapshot
High-performance multi-queue buffers for VLSI communications switches
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.5555/602770.602887openalex-snapshot
Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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On-Chip Networks for Multicore Systems
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Reconfigurable Intercommunication Infrastructure: NoCs
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Communication Architecture
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Virtual-Channel Flow Control and Buffering
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Multi-Core Cache Hierarchies
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A Systematic Literature Review of Network-on-Chip Architectures: Topologies, Routing, Reliability, and Emerging Technologies
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Efficient Buffer Design and Implementation for Wormhole Routers on FPGAs
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Congestion Aware Routing for On-Chip Communication in NoC Systems
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A Virtual Channel Allocation Algorithm for NoC
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Design of 8-Bit Programmable Crossbar Switch for Network-on-Chip Router
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Energy-Aware On-Chip Networks
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Latency Improvement by Using Fill VC Allocation for Network on Chip
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CRAFT: Common Router Architecture for Throughput Optimization
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RIDER: Ring deflection router with buffers
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Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion
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Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks
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Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip
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A highly efficient dynamic router for application-oriented network on chip
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Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC
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PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
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An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network
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Runtime buffer management to improve the performance in irregular Network-on-Chip architecture
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A Traffic Intensive Virtual Channels Allocation Scheme in Network-on-Chip
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Dynamic virtual channel routers with congestion awareness††Part of this research was first presented at the 45th Design Automation Conference (DAC-2008) [19] and the 29th International Conference of Computer Design (ICCD-2011) [33].
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Flow control for fully adaptive routing††Part of this research was first presented at the 18th IEEE International Symposium on High Performance Computer Architecture (HPCA-2012) [32]. The journal extension edition of the HPCA-2012 paper was published in IEEE Transactions on Parallel and…
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Deadlock-free flow control for torus networks-on-chip††Part of this research was first published in IEEE Transactions on Computers [39].
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Dark Silicon and the History of Computing
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Topology Specialization for Networks-on-Chip in the Dark Silicon Era
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A power-performance balanced network-on-chip for mixed CPU-GPU systems
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Routerless networks-on-chip
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A congestion-aware routing algorithm for mesh-based platform networks-on-chip
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A practical low-latency router architecture with wing channel for on-chip network
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Exploiting and evaluating the potentials of the link addition method for NoC transient error mitigation
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Statically adaptive multi FIFO buffer architecture for network on chip
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SDNoC: Software defined network on a chip
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Accelerated assessment of fine-grain AVF in NoC using a Multi-Cell Upsets considered fault injection
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A novel congestion-aware routing algorithm with prediction in mesh-based networks-on-chip
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Packet-based Adaptive Virtual Channel Configuration for NoC Systems
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Novel flexible buffering architectures for 3D-NoCs
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Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip
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Lessen Interflow Interference Using Virtual Channels Partitioning
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Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective
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A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study
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Variation-Aware Low-Power Buffer Design
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Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip
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Dynamic virtual channel and index-based arbitration based Network on Chip router architecture
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Adaptive allocation of default router paths in Network-on-Chips for latency reduction
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An Adaptive Routing Algorithm for on-chip 2D Mesh Network with an Efficient Buffer Allocation Scheme
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Efficient Dynamic Virtual Channel Architecture for NoC Systems
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Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
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Defect-tolerant routing algorithm for low power NoCs based on buffer-shared router architecture
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A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer
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Adaptive Backpressure: Efficient buffer management for on-chip networks
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Reconfigurable router design for Network-on-Chip
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Efficient Dynamic Router Architecture for Optimized Performance of NoC Systems
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NoC-based many-core processor using CUSPARC architecture
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Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip
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Wormhole routing optimization algorithm based on virtual channel switching
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Dynamic buffer management to improve the performance of fault tolerance adaptive Network-On-Chip applications
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Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs
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MIRA: A Multi-layered On-Chip Interconnect Router Architecture
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Power-aware NoC router using central forecasting-based dynamic virtual channel allocation
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Reconfigurable router using RLBS algorithm
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Dynamic NoC platform for varied application needs
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Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability
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Loopback Virtual Channel Router Architecture for Network on Chip
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Congestion mitigation using flexible router architecture for Network-on-Chip
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A High-Throughput Distributed Shared-Buffer NoC Router
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Self-Adaptive Network-on-Chip Interface
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Dynamic VC Organization for Efficient NoC Communication
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Adaptive VC Organization and Arbitration for Efficient NoC Design
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SPOCK: Reverse Packet Traversal for Deadlock Recovery
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Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
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Flattened Butterfly Topology for On-Chip Networks
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Efficient Router Bypass via Hybrid Flow Control
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Approaching Ideal NoC Latency with Pre-Configured Routes
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QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
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Evaluating Bufferless Flow Control for On-chip Networks
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Design of a High-Throughput Distributed Shared-Buffer NoC Router
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Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels
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PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs
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A speculative arbiter design to enable high-frequency many-VC router in NoCs
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Design of a low power NoC router using Marching Memory Through type
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Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
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Multi-Swarm based NoC Configuration and Synthesis
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A review of dynamic power management methods in NoC under emerging design considerations
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QoS router with both soft and hard guarantee for Network-on-Chip
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Design and Evaluation of Dynamically-Allocated Multi-queue Buffers with Multiple Packets for NoC Routers
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Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
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3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip
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Simple and Effective Adaptive Routing Algorithms in Multi-Layer Wormhole Networks
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PVS-NoC: Partial Virtual Channel Sharing NoC Architecture
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A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing
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Key Research Issues for Reconfigurable Network-on-Chip
inferred← citeshttps://doi.org/10.1109/sbac-padw.2014.16openalex-snapshot
Efficient Virtual Channel Organization and Congestion Avoidance in Multicore NoC Systems
inferred← citeshttps://doi.org/10.1109/sc.2018.00007openalex-snapshot
Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage
inferred← citeshttps://doi.org/10.1109/socc.2017.8226030openalex-snapshot
Efficient virtual channel allocator for NoC router micro-architecture
inferred← citeshttps://doi.org/10.1109/spin.2017.8049926openalex-snapshot
Route-on-Fly: A single cycle router
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Virtual channel router architecture for Network on Chip with adaptive inter-port buffers sharing
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Buffers Sharing Switch Design Exploiting Dynamic Traffic Orientation in a NoC
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Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
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MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects
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Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs
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Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems
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Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1109/tc.2017.2705141openalex-snapshot
A Dual-Clock Multiple-Queue Shared Buffer
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
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Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers
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Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance
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Enhancing Network-on-Chip Performance by Reusing Trace Buffers
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DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip
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Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design
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ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC Based MPSoCs
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Balancing Performance and Cost in CMP Interconnection Networks
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Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs
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Heterogeneous NoC Router Architecture
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CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs
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SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design
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Reconfigurable Routers for Low Power and High Performance
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AdNoC: Runtime Adaptive Network-on-Chip Architecture
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Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips
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Achieving High-Performance On-Chip Networks With Shared-Buffer Routers
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FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels
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ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip
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Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems
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Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC
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Traffic-aware buffer reconfiguration in on-chip networks
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Highly efficient reconfigurable routers in Networks-on-Chip
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Two-levels of adaptive buffer for virtual channel router in NoCs
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An Adaptive Approach to Manage the Number of Virtual Channels
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AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip
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Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip
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Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
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A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
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